merge custom cell and module properties

compiler/base/custom_cell_properties.py

@@ -5,6 +5,15 @@
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
 #
+class _mirror_axis:
+    def __init__(self, x, y):
+        self.x = x
+        self.y = y
+
+class _bitcell:
+    def __init__(self, mirror, split_wl):
+        self.mirror = mirror
+        self.split_wl = split_wl
 
 class _dff:
     def __init__(self, use_custom_ports, custom_port_list, custom_type_list, clk_pin):
@@ -24,13 +33,16 @@ class _dff_buff_array:
         self.use_custom_ports = use_custom_ports
         self.add_body_contacts = add_body_contacts
 
-class module_properties():
+class cell_properties():
     """
     TODO
     """
     def __init__(self):
         self.names = {}
 
+        self._bitcell = _bitcell(mirror = _mirror_axis(True, False),
+                                 split_wl = False)
+                                 
         self._dff = _dff(use_custom_ports = False,
                          custom_port_list = ["D", "Q", "clk", "vdd", "gnd"],
                          custom_type_list = ["INPUT", "OUTPUT", "INPUT", "POWER", "GROUND"],
@@ -43,6 +55,10 @@ class module_properties():
         self._dff_buff_array = _dff_buff_array(use_custom_ports = False,
                                                add_body_contacts = False)
 
+    @property
+    def bitcell(self):
+        return self._bitcell
+
     @property
     def dff(self):
         return self._dff
@@ -54,3 +70,4 @@ class module_properties():
     @property
     def dff_buff_array(self):
         return self._dff_buff_array
+

compiler/bitcells/custom_cell_properties.py

@@ -1,30 +0,0 @@
-# See LICENSE for licensing information.
-#
-# Copyright (c) 2016-2020 Regents of the University of California and The Board
-# of Regents for the Oklahoma Agricultural and Mechanical College
-# (acting for and on behalf of Oklahoma State University)
-# All rights reserved.
-#
-
-class _mirror_axis:
-    def __init__(self, x, y):
-        self.x = x
-        self.y = y
-
-class _bitcell:
-    def __init__(self, mirror, split_wl):
-        self.mirror = mirror
-        self.split_wl = split_wl
-
-class cell_properties():
-    """
-    TODO
-    """
-    def __init__(self):
-        self.names = {}
-        self._bitcell = _bitcell(mirror = _mirror_axis(True, False),
-                                 split_wl = False)
-
-    @property
-    def bitcell(self):
-        return self._bitcell

compiler/modules/control_logic.py

@@ -7,7 +7,8 @@
 #
 from math import log
 import design
-from tech import drc, parameter, module_properties
+from tech import drc, parameter
+from tech import cell_properties as props
 import debug
 import contact
 from sram_factory import factory
@@ -743,7 +744,7 @@ class control_logic(design.design):
         self.ctrl_dff_inst=self.add_inst(name="ctrl_dffs",
                                          mod=self.ctrl_dff_array)
         inst_pins = self.input_list + self.dff_output_list + ["clk_buf"] + self.supply_list
-        if module_properties.dff_buff_array.add_body_contacts:
+        if props.dff_buff_array.add_body_contacts:
             inst_pins.append("vpb")
             inst_pins.append("vnb")
         self.connect_inst(inst_pins)

compiler/modules/dff.py

@@ -7,7 +7,7 @@
 #
 import design
 from tech import GDS, layer, spice, parameter
-from tech import module_properties
+from tech import cell_properties as props
 import utils
 
 
@@ -15,14 +15,14 @@ class dff(design.design):
     """
     Memory address flip-flop
     """
-    if not module_properties.dff.use_custom_ports:
+    if not props.dff.use_custom_ports:
         pin_names = ["D", "Q", "clk", "vdd", "gnd"]
         type_list = ["INPUT", "OUTPUT", "INPUT", "POWER", "GROUND"]
         clk_pin = "clk"
     else:
-        pin_names = module_properties.dff.custom_port_list
+        pin_names = props.dff.custom_port_list
-        type_list = module_properties.dff.custom_type_list
+        type_list = props.dff.custom_type_list
-        clk_pin = module_properties.dff.clk_pin
+        clk_pin = props.dff.clk_pin
 
     (width, height) = utils.get_libcell_size("dff",
                                              GDS["unit"],

compiler/modules/dff_buf.py

@@ -7,7 +7,8 @@
 #
 import debug
 import design
-from tech import drc,parameter,module_properties
+from tech import drc,parameter
+from tech import cell_properties as props
 from math import log
 from vector import vector
 from globals import OPTS
@@ -82,14 +83,14 @@ class dff_buf(design.design):
         self.add_pin("vdd", "POWER")
         self.add_pin("gnd", "GROUND")
 
-        if module_properties.dff_buff.add_body_contacts:
+        if props.dff_buff.add_body_contacts:
             self.add_pin("vpb", "INPUT")
             self.add_pin("vpn", "INPUT")
 
     def create_instances(self):
         self.dff_inst=self.add_inst(name="dff_buf_dff",
                                     mod=self.dff)
-        self.connect_inst(module_properties.dff_buff.buf_ports)                                    
+        self.connect_inst(props.dff_buff.buf_ports)                                    
         #self.connect_inst(["D", "qint", "clk", "vdd", "gnd"])
 
         self.inv1_inst=self.add_inst(name="dff_buf_inv1",

compiler/modules/dff_buf_array.py

@@ -7,7 +7,8 @@
 #
 import debug
 import design
-from tech import drc, module_properties
+from tech import drc
+from tech import cell_properties as props
 from math import log
 from vector import vector
 from globals import OPTS
@@ -64,7 +65,7 @@ class dff_buf_array(design.design):
         self.add_pin("vdd", "POWER")
         self.add_pin("gnd", "GROUND")
 
-        if module_properties.dff_buff_array.add_body_contacts:
+        if props.dff_buff_array.add_body_contacts:
             self.add_pin("vpb", "INPUT")
             self.add_pin("vnb", "INPUT")
 
@@ -87,7 +88,7 @@ class dff_buf_array(design.design):
                                    "clk",
                                    "vdd",
                                    "gnd"]
-                if module_properties.dff_buff_array.add_body_contacts:
+                if props.dff_buff_array.add_body_contacts:
                     inst_ports.append("vpb")
                     inst_ports.append("vnb")
                 self.connect_inst(inst_ports)

technology/freepdk45/tech/tech.py

@@ -9,7 +9,7 @@ import os
 from design_rules import *
 from module_type import *
 from custom_cell_properties import cell_properties
-from custom_module_properties import module_properties
+
 """
 File containing the process technology parameters for FreePDK 45nm.
 """
@@ -25,7 +25,7 @@ File containing the process technology parameters for FreePDK 45nm.
 # For example: tech_modules['contact'] = 'contact_freepdk45'
 tech_modules = module_type()
 
-module_properties = module_properties()
+
 ###################################################
 # Custom cell properties
 ###################################################

technology/scn4m_subm/tech/tech.py

@@ -9,7 +9,6 @@ import os
 from design_rules import *
 from module_type import *
 from custom_cell_properties import cell_properties
-from custom_module_properties import module_properties
 
 """
 File containing the process technology parameters for SCMOS 4m, 0.35um
@@ -25,7 +24,6 @@ File containing the process technology parameters for SCMOS 4m, 0.35um
 # implementation in '$OPENRAM_TECHDIR/modules/'
 # For example: tech_modules['contact'] = 'contact_scn4m'
 tech_modules = module_type()
-module_properties = module_properties()
 
 ###################################################
 # Custom cell properties