From aedbc5f9689ba1b8fd4577b77f4f41b9a04b67d9 Mon Sep 17 00:00:00 2001 From: Jesse Cirimelli-Low Date: Wed, 12 Feb 2020 04:09:40 +0000 Subject: [PATCH] merge custom cell and module properties --- .../custom_cell_properties.py} | 23 ++++++++++++-- compiler/bitcells/custom_cell_properties.py | 30 ------------------- compiler/modules/control_logic.py | 5 ++-- compiler/modules/dff.py | 10 +++---- compiler/modules/dff_buf.py | 7 +++-- compiler/modules/dff_buf_array.py | 7 +++-- technology/freepdk45/tech/tech.py | 4 +-- technology/scn4m_subm/tech/tech.py | 2 -- 8 files changed, 38 insertions(+), 50 deletions(-) rename compiler/{modules/custom_module_properties.py => base/custom_cell_properties.py} (79%) delete mode 100644 compiler/bitcells/custom_cell_properties.py diff --git a/compiler/modules/custom_module_properties.py b/compiler/base/custom_cell_properties.py similarity index 79% rename from compiler/modules/custom_module_properties.py rename to compiler/base/custom_cell_properties.py index 768a8c18..ed00d443 100644 --- a/compiler/modules/custom_module_properties.py +++ b/compiler/base/custom_cell_properties.py @@ -5,6 +5,15 @@ # (acting for and on behalf of Oklahoma State University) # All rights reserved. # +class _mirror_axis: + def __init__(self, x, y): + self.x = x + self.y = y + +class _bitcell: + def __init__(self, mirror, split_wl): + self.mirror = mirror + self.split_wl = split_wl class _dff: def __init__(self, use_custom_ports, custom_port_list, custom_type_list, clk_pin): @@ -24,13 +33,16 @@ class _dff_buff_array: self.use_custom_ports = use_custom_ports self.add_body_contacts = add_body_contacts -class module_properties(): +class cell_properties(): """ TODO """ def __init__(self): self.names = {} - + + self._bitcell = _bitcell(mirror = _mirror_axis(True, False), + split_wl = False) + self._dff = _dff(use_custom_ports = False, custom_port_list = ["D", "Q", "clk", "vdd", "gnd"], custom_type_list = ["INPUT", "OUTPUT", "INPUT", "POWER", "GROUND"], @@ -43,6 +55,10 @@ class module_properties(): self._dff_buff_array = _dff_buff_array(use_custom_ports = False, add_body_contacts = False) + @property + def bitcell(self): + return self._bitcell + @property def dff(self): return self._dff @@ -53,4 +69,5 @@ class module_properties(): @property def dff_buff_array(self): - return self._dff_buff_array \ No newline at end of file + return self._dff_buff_array + diff --git a/compiler/bitcells/custom_cell_properties.py b/compiler/bitcells/custom_cell_properties.py deleted file mode 100644 index e795f6d7..00000000 --- a/compiler/bitcells/custom_cell_properties.py +++ /dev/null @@ -1,30 +0,0 @@ -# See LICENSE for licensing information. -# -# Copyright (c) 2016-2020 Regents of the University of California and The Board -# of Regents for the Oklahoma Agricultural and Mechanical College -# (acting for and on behalf of Oklahoma State University) -# All rights reserved. -# - -class _mirror_axis: - def __init__(self, x, y): - self.x = x - self.y = y - -class _bitcell: - def __init__(self, mirror, split_wl): - self.mirror = mirror - self.split_wl = split_wl - -class cell_properties(): - """ - TODO - """ - def __init__(self): - self.names = {} - self._bitcell = _bitcell(mirror = _mirror_axis(True, False), - split_wl = False) - - @property - def bitcell(self): - return self._bitcell diff --git a/compiler/modules/control_logic.py b/compiler/modules/control_logic.py index fa11e30b..e22d05b3 100644 --- a/compiler/modules/control_logic.py +++ b/compiler/modules/control_logic.py @@ -7,7 +7,8 @@ # from math import log import design -from tech import drc, parameter, module_properties +from tech import drc, parameter +from tech import cell_properties as props import debug import contact from sram_factory import factory @@ -743,7 +744,7 @@ class control_logic(design.design): self.ctrl_dff_inst=self.add_inst(name="ctrl_dffs", mod=self.ctrl_dff_array) inst_pins = self.input_list + self.dff_output_list + ["clk_buf"] + self.supply_list - if module_properties.dff_buff_array.add_body_contacts: + if props.dff_buff_array.add_body_contacts: inst_pins.append("vpb") inst_pins.append("vnb") self.connect_inst(inst_pins) diff --git a/compiler/modules/dff.py b/compiler/modules/dff.py index 45d20a62..e319459e 100644 --- a/compiler/modules/dff.py +++ b/compiler/modules/dff.py @@ -7,7 +7,7 @@ # import design from tech import GDS, layer, spice, parameter -from tech import module_properties +from tech import cell_properties as props import utils @@ -15,14 +15,14 @@ class dff(design.design): """ Memory address flip-flop """ - if not module_properties.dff.use_custom_ports: + if not props.dff.use_custom_ports: pin_names = ["D", "Q", "clk", "vdd", "gnd"] type_list = ["INPUT", "OUTPUT", "INPUT", "POWER", "GROUND"] clk_pin = "clk" else: - pin_names = module_properties.dff.custom_port_list - type_list = module_properties.dff.custom_type_list - clk_pin = module_properties.dff.clk_pin + pin_names = props.dff.custom_port_list + type_list = props.dff.custom_type_list + clk_pin = props.dff.clk_pin (width, height) = utils.get_libcell_size("dff", GDS["unit"], diff --git a/compiler/modules/dff_buf.py b/compiler/modules/dff_buf.py index d2698b34..1fba563b 100644 --- a/compiler/modules/dff_buf.py +++ b/compiler/modules/dff_buf.py @@ -7,7 +7,8 @@ # import debug import design -from tech import drc,parameter,module_properties +from tech import drc,parameter +from tech import cell_properties as props from math import log from vector import vector from globals import OPTS @@ -82,14 +83,14 @@ class dff_buf(design.design): self.add_pin("vdd", "POWER") self.add_pin("gnd", "GROUND") - if module_properties.dff_buff.add_body_contacts: + if props.dff_buff.add_body_contacts: self.add_pin("vpb", "INPUT") self.add_pin("vpn", "INPUT") def create_instances(self): self.dff_inst=self.add_inst(name="dff_buf_dff", mod=self.dff) - self.connect_inst(module_properties.dff_buff.buf_ports) + self.connect_inst(props.dff_buff.buf_ports) #self.connect_inst(["D", "qint", "clk", "vdd", "gnd"]) self.inv1_inst=self.add_inst(name="dff_buf_inv1", diff --git a/compiler/modules/dff_buf_array.py b/compiler/modules/dff_buf_array.py index 326fdda1..770675bf 100644 --- a/compiler/modules/dff_buf_array.py +++ b/compiler/modules/dff_buf_array.py @@ -7,7 +7,8 @@ # import debug import design -from tech import drc, module_properties +from tech import drc +from tech import cell_properties as props from math import log from vector import vector from globals import OPTS @@ -64,7 +65,7 @@ class dff_buf_array(design.design): self.add_pin("vdd", "POWER") self.add_pin("gnd", "GROUND") - if module_properties.dff_buff_array.add_body_contacts: + if props.dff_buff_array.add_body_contacts: self.add_pin("vpb", "INPUT") self.add_pin("vnb", "INPUT") @@ -87,7 +88,7 @@ class dff_buf_array(design.design): "clk", "vdd", "gnd"] - if module_properties.dff_buff_array.add_body_contacts: + if props.dff_buff_array.add_body_contacts: inst_ports.append("vpb") inst_ports.append("vnb") self.connect_inst(inst_ports) diff --git a/technology/freepdk45/tech/tech.py b/technology/freepdk45/tech/tech.py index f91be16c..c2bf135f 100644 --- a/technology/freepdk45/tech/tech.py +++ b/technology/freepdk45/tech/tech.py @@ -9,7 +9,7 @@ import os from design_rules import * from module_type import * from custom_cell_properties import cell_properties -from custom_module_properties import module_properties + """ File containing the process technology parameters for FreePDK 45nm. """ @@ -25,7 +25,7 @@ File containing the process technology parameters for FreePDK 45nm. # For example: tech_modules['contact'] = 'contact_freepdk45' tech_modules = module_type() -module_properties = module_properties() + ################################################### # Custom cell properties ################################################### diff --git a/technology/scn4m_subm/tech/tech.py b/technology/scn4m_subm/tech/tech.py index bb379478..7c360d38 100644 --- a/technology/scn4m_subm/tech/tech.py +++ b/technology/scn4m_subm/tech/tech.py @@ -9,7 +9,6 @@ import os from design_rules import * from module_type import * from custom_cell_properties import cell_properties -from custom_module_properties import module_properties """ File containing the process technology parameters for SCMOS 4m, 0.35um @@ -25,7 +24,6 @@ File containing the process technology parameters for SCMOS 4m, 0.35um # implementation in '$OPENRAM_TECHDIR/modules/' # For example: tech_modules['contact'] = 'contact_scn4m' tech_modules = module_type() -module_properties = module_properties() ################################################### # Custom cell properties