mirror of https://github.com/VLSIDA/OpenRAM.git
Fix base class error
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@ -8,12 +8,10 @@
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import debug
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import debug
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import bitcell_base
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import bitcell_base
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from tech import cell_properties as props
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from tech import cell_properties as props
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from tech import GDS, layer
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from globals import OPTS
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from globals import OPTS
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import utils
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class replica_bitcell_1rw_1r(bitcell_base):
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class replica_bitcell_1rw_1r(bitcell_base.bitcell_base):
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"""
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"""
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A single bit cell which is forced to store a 0.
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A single bit cell which is forced to store a 0.
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This module implements the single memory cell used in the design. It
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This module implements the single memory cell used in the design. It
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