Merge remote-tracking branch 'private/dev' into dev

.github/workflows/ci.yml

@@ -12,7 +12,7 @@ jobs:
          export OPENRAM_HOME="`pwd`/compiler"
          export OPENRAM_TECH="`pwd`/technology:/software/PDKs/skywater-tech"
          export OPENRAM_TMP="`pwd`/scn4me_subm"
-         python3-coverage run -p $OPENRAM_HOME/tests/regress.py -j 20 -t scn4m_subm
+         python3-coverage run -p $OPENRAM_HOME/tests/regress.py -j 48 -t scn4m_subm
       - name: Archive
         if: ${{ failure() }}
         uses: actions/upload-artifact@v2
@@ -30,7 +30,7 @@ jobs:
          export OPENRAM_HOME="`pwd`/compiler"
          export OPENRAM_TECH="`pwd`/technology:/software/PDKs/skywater-tech"
          export OPENRAM_TMP="`pwd`/freepdk45"
-         python3-coverage run -p $OPENRAM_HOME/tests/regress.py -j 20 -t freepdk45
+         python3-coverage run -p $OPENRAM_HOME/tests/regress.py -j 48 -t freepdk45
       - name: Archive
         if: ${{ failure() }}
         uses: actions/upload-artifact@v2

README.md

@@ -4,13 +4,9 @@
 [![License: BSD 3-clause](./images/license_badge.svg)](./LICENSE)
 
 Master: 
-[![Pipeline Status](https://scone.soe.ucsc.edu:8888/mrg/OpenRAM/badges/master/pipeline.svg)](https://github.com/VLSIDA/OpenRAM/commits/master)
-![Coverage](https://scone.soe.ucsc.edu:8888/mrg/OpenRAM/badges/master/coverage.svg)
 [![Download](./images/download-stable-blue.svg)](https://github.com/VLSIDA/OpenRAM/archive/master.zip)
 
 Dev: 
-[![Pipeline Status](https://scone.soe.ucsc.edu:8888/mrg/OpenRAM/badges/dev/pipeline.svg)](https://github.com/VLSIDA/OpenRAM/commits/dev)
-![Coverage](https://scone.soe.ucsc.edu:8888/mrg/OpenRAM/badges/dev/coverage.svg)
 [![Download](./images/download-unstable-blue.svg)](https://github.com/VLSIDA/OpenRAM/archive/dev.zip)
 
 An open-source static random access memory (SRAM) compiler.

compiler/characterizer/lib.py

@@ -236,10 +236,9 @@ class lib:
         self.lib.write("    slew_lower_threshold_pct_rise  :  10.0 ;\n")
         self.lib.write("    slew_upper_threshold_pct_rise  :  90.0 ;\n\n")
 
-        self.lib.write("    nom_voltage : {};\n".format(tech.spice["nom_supply_voltage"]))
+        self.lib.write("    nom_voltage : {};\n".format(self.voltage))
-        self.lib.write("    nom_temperature : {};\n".format(tech.spice["nom_temperature"]))
+        self.lib.write("    nom_temperature : {};\n".format(self.temperature))
-        self.lib.write("    nom_process : {};\n".format(1.0))
+        self.lib.write("    nom_process : 1.0;\n")
-
         self.lib.write("    default_cell_leakage_power    : 0.0 ;\n")
         self.lib.write("    default_leakage_power_density : 0.0 ;\n")
         self.lib.write("    default_input_pin_cap    : 1.0 ;\n")
@@ -250,7 +249,7 @@ class lib:
         self.lib.write("    default_max_fanout   : 4.0 ;\n")
         self.lib.write("    default_connection_class : universal ;\n\n")
 
-        self.lib.write("    voltage_map ( VDD, {} );\n".format(tech.spice["nom_supply_voltage"]))
+        self.lib.write("    voltage_map ( VDD, {} );\n".format(self.voltage))
         self.lib.write("    voltage_map ( GND, 0 );\n\n")
 
     def create_list(self,values):

compiler/example_configs/riscv_sky130_1kbyte_1rw1r.py

@@ -2,7 +2,7 @@ word_size = 32
 num_words = 256
 write_size = 8
 
-local_array_size = 16
+#local_array_size = 16
 
 num_rw_ports = 1
 num_r_ports = 1
@@ -11,9 +11,9 @@ num_w_ports = 0
 tech_name = "sky130"
 nominal_corner_only = True
 
-route_supplies = False
+#route_supplies = False
 check_lvsdrc = True
-perimeter_pins = False
+#perimeter_pins = False
 #netlist_only = True
 #analytical_delay = False
 output_name = "sram_{0}rw{1}r{2}w_{3}_{4}_{5}".format(num_rw_ports,