From b0c27225838ab78ca038cd44db9704de150ba1b6 Mon Sep 17 00:00:00 2001 From: Hunter Nichols Date: Tue, 19 Jan 2021 15:22:50 -0800 Subject: [PATCH 1/7] Changed lib file to only contain reference to the operating voltage and removed nominal voltage references. --- compiler/characterizer/lib.py | 6 +----- 1 file changed, 1 insertion(+), 5 deletions(-) diff --git a/compiler/characterizer/lib.py b/compiler/characterizer/lib.py index e5628c5d..9040f2e3 100644 --- a/compiler/characterizer/lib.py +++ b/compiler/characterizer/lib.py @@ -224,10 +224,6 @@ class lib: self.lib.write(" slew_lower_threshold_pct_rise : 10.0 ;\n") self.lib.write(" slew_upper_threshold_pct_rise : 90.0 ;\n\n") - self.lib.write(" nom_voltage : {};\n".format(tech.spice["nom_supply_voltage"])) - self.lib.write(" nom_temperature : {};\n".format(tech.spice["nom_temperature"])) - self.lib.write(" nom_process : {};\n".format(1.0)) - self.lib.write(" default_cell_leakage_power : 0.0 ;\n") self.lib.write(" default_leakage_power_density : 0.0 ;\n") self.lib.write(" default_input_pin_cap : 1.0 ;\n") @@ -238,7 +234,7 @@ class lib: self.lib.write(" default_max_fanout : 4.0 ;\n") self.lib.write(" default_connection_class : universal ;\n\n") - self.lib.write(" voltage_map ( VDD, {} );\n".format(tech.spice["nom_supply_voltage"])) + self.lib.write(" voltage_map ( VDD, {} );\n".format(self.voltage)) self.lib.write(" voltage_map ( GND, 0 );\n\n") def create_list(self,values): From 31ad1963f67499a30d3235c67059d1fbd8f7ec14 Mon Sep 17 00:00:00 2001 From: Hunter Nichols Date: Thu, 21 Jan 2021 12:47:18 -0800 Subject: [PATCH 2/7] Removed nominal pvt corners from golden lib files. --- .../golden/sram_2_16_1_freepdk45_FF_1p0V_25C_analytical.lib | 3 --- .../golden/sram_2_16_1_freepdk45_SS_1p0V_25C_analytical.lib | 3 --- compiler/tests/golden/sram_2_16_1_freepdk45_TT_1p0V_25C.lib | 3 --- .../golden/sram_2_16_1_freepdk45_TT_1p0V_25C_analytical.lib | 3 --- .../tests/golden/sram_2_16_1_freepdk45_TT_1p0V_25C_pruned.lib | 3 --- .../golden/sram_2_16_1_scn4m_subm_FF_5p0V_25C_analytical.lib | 3 --- .../golden/sram_2_16_1_scn4m_subm_SS_5p0V_25C_analytical.lib | 3 --- compiler/tests/golden/sram_2_16_1_scn4m_subm_TT_5p0V_25C.lib | 3 --- .../golden/sram_2_16_1_scn4m_subm_TT_5p0V_25C_analytical.lib | 3 --- .../tests/golden/sram_2_16_1_scn4m_subm_TT_5p0V_25C_pruned.lib | 3 --- 10 files changed, 30 deletions(-) diff --git a/compiler/tests/golden/sram_2_16_1_freepdk45_FF_1p0V_25C_analytical.lib b/compiler/tests/golden/sram_2_16_1_freepdk45_FF_1p0V_25C_analytical.lib index b3ef0e0a..6ba1e114 100644 --- a/compiler/tests/golden/sram_2_16_1_freepdk45_FF_1p0V_25C_analytical.lib +++ b/compiler/tests/golden/sram_2_16_1_freepdk45_FF_1p0V_25C_analytical.lib @@ -22,9 +22,6 @@ library (sram_2_16_1_freepdk45_FF_1p0V_25C_lib){ slew_lower_threshold_pct_rise : 10.0 ; slew_upper_threshold_pct_rise : 90.0 ; - nom_voltage : 1.0; - nom_temperature : 25; - nom_process : 1.0; default_cell_leakage_power : 0.0 ; default_leakage_power_density : 0.0 ; default_input_pin_cap : 1.0 ; diff --git a/compiler/tests/golden/sram_2_16_1_freepdk45_SS_1p0V_25C_analytical.lib b/compiler/tests/golden/sram_2_16_1_freepdk45_SS_1p0V_25C_analytical.lib index 34be4fe4..2bde8e2b 100644 --- a/compiler/tests/golden/sram_2_16_1_freepdk45_SS_1p0V_25C_analytical.lib +++ b/compiler/tests/golden/sram_2_16_1_freepdk45_SS_1p0V_25C_analytical.lib @@ -22,9 +22,6 @@ library (sram_2_16_1_freepdk45_SS_1p0V_25C_lib){ slew_lower_threshold_pct_rise : 10.0 ; slew_upper_threshold_pct_rise : 90.0 ; - nom_voltage : 1.0; - nom_temperature : 25; - nom_process : 1.0; default_cell_leakage_power : 0.0 ; default_leakage_power_density : 0.0 ; default_input_pin_cap : 1.0 ; diff --git a/compiler/tests/golden/sram_2_16_1_freepdk45_TT_1p0V_25C.lib b/compiler/tests/golden/sram_2_16_1_freepdk45_TT_1p0V_25C.lib index cca9c1ed..82231d5d 100644 --- a/compiler/tests/golden/sram_2_16_1_freepdk45_TT_1p0V_25C.lib +++ b/compiler/tests/golden/sram_2_16_1_freepdk45_TT_1p0V_25C.lib @@ -22,9 +22,6 @@ library (sram_2_16_1_freepdk45_TT_1p0V_25C_lib){ slew_lower_threshold_pct_rise : 10.0 ; slew_upper_threshold_pct_rise : 90.0 ; - nom_voltage : 1.0; - nom_temperature : 25; - nom_process : 1.0; default_cell_leakage_power : 0.0 ; default_leakage_power_density : 0.0 ; default_input_pin_cap : 1.0 ; diff --git a/compiler/tests/golden/sram_2_16_1_freepdk45_TT_1p0V_25C_analytical.lib b/compiler/tests/golden/sram_2_16_1_freepdk45_TT_1p0V_25C_analytical.lib index 26028892..3f79ce08 100644 --- a/compiler/tests/golden/sram_2_16_1_freepdk45_TT_1p0V_25C_analytical.lib +++ b/compiler/tests/golden/sram_2_16_1_freepdk45_TT_1p0V_25C_analytical.lib @@ -22,9 +22,6 @@ library (sram_2_16_1_freepdk45_TT_1p0V_25C_lib){ slew_lower_threshold_pct_rise : 10.0 ; slew_upper_threshold_pct_rise : 90.0 ; - nom_voltage : 1.0; - nom_temperature : 25; - nom_process : 1.0; default_cell_leakage_power : 0.0 ; default_leakage_power_density : 0.0 ; default_input_pin_cap : 1.0 ; diff --git a/compiler/tests/golden/sram_2_16_1_freepdk45_TT_1p0V_25C_pruned.lib b/compiler/tests/golden/sram_2_16_1_freepdk45_TT_1p0V_25C_pruned.lib index 5817211b..bdaeab71 100644 --- a/compiler/tests/golden/sram_2_16_1_freepdk45_TT_1p0V_25C_pruned.lib +++ b/compiler/tests/golden/sram_2_16_1_freepdk45_TT_1p0V_25C_pruned.lib @@ -22,9 +22,6 @@ library (sram_2_16_1_freepdk45_TT_1p0V_25C_lib){ slew_lower_threshold_pct_rise : 10.0 ; slew_upper_threshold_pct_rise : 90.0 ; - nom_voltage : 1.0; - nom_temperature : 25; - nom_process : 1.0; default_cell_leakage_power : 0.0 ; default_leakage_power_density : 0.0 ; default_input_pin_cap : 1.0 ; diff --git a/compiler/tests/golden/sram_2_16_1_scn4m_subm_FF_5p0V_25C_analytical.lib b/compiler/tests/golden/sram_2_16_1_scn4m_subm_FF_5p0V_25C_analytical.lib index 6912aec7..c9d811b4 100644 --- a/compiler/tests/golden/sram_2_16_1_scn4m_subm_FF_5p0V_25C_analytical.lib +++ b/compiler/tests/golden/sram_2_16_1_scn4m_subm_FF_5p0V_25C_analytical.lib @@ -22,9 +22,6 @@ library (sram_2_16_1_scn4m_subm_FF_5p0V_25C_lib){ slew_lower_threshold_pct_rise : 10.0 ; slew_upper_threshold_pct_rise : 90.0 ; - nom_voltage : 5.0; - nom_temperature : 25; - nom_process : 1.0; default_cell_leakage_power : 0.0 ; default_leakage_power_density : 0.0 ; default_input_pin_cap : 1.0 ; diff --git a/compiler/tests/golden/sram_2_16_1_scn4m_subm_SS_5p0V_25C_analytical.lib b/compiler/tests/golden/sram_2_16_1_scn4m_subm_SS_5p0V_25C_analytical.lib index a7605cb3..605f88cc 100644 --- a/compiler/tests/golden/sram_2_16_1_scn4m_subm_SS_5p0V_25C_analytical.lib +++ b/compiler/tests/golden/sram_2_16_1_scn4m_subm_SS_5p0V_25C_analytical.lib @@ -22,9 +22,6 @@ library (sram_2_16_1_scn4m_subm_SS_5p0V_25C_lib){ slew_lower_threshold_pct_rise : 10.0 ; slew_upper_threshold_pct_rise : 90.0 ; - nom_voltage : 5.0; - nom_temperature : 25; - nom_process : 1.0; default_cell_leakage_power : 0.0 ; default_leakage_power_density : 0.0 ; default_input_pin_cap : 1.0 ; diff --git a/compiler/tests/golden/sram_2_16_1_scn4m_subm_TT_5p0V_25C.lib b/compiler/tests/golden/sram_2_16_1_scn4m_subm_TT_5p0V_25C.lib index 8bec74c3..b416f3b5 100644 --- a/compiler/tests/golden/sram_2_16_1_scn4m_subm_TT_5p0V_25C.lib +++ b/compiler/tests/golden/sram_2_16_1_scn4m_subm_TT_5p0V_25C.lib @@ -22,9 +22,6 @@ library (sram_2_16_1_scn4m_subm_TT_5p0V_25C_lib){ slew_lower_threshold_pct_rise : 10.0 ; slew_upper_threshold_pct_rise : 90.0 ; - nom_voltage : 5.0; - nom_temperature : 25; - nom_process : 1.0; default_cell_leakage_power : 0.0 ; default_leakage_power_density : 0.0 ; default_input_pin_cap : 1.0 ; diff --git a/compiler/tests/golden/sram_2_16_1_scn4m_subm_TT_5p0V_25C_analytical.lib b/compiler/tests/golden/sram_2_16_1_scn4m_subm_TT_5p0V_25C_analytical.lib index 8bec74c3..b416f3b5 100644 --- a/compiler/tests/golden/sram_2_16_1_scn4m_subm_TT_5p0V_25C_analytical.lib +++ b/compiler/tests/golden/sram_2_16_1_scn4m_subm_TT_5p0V_25C_analytical.lib @@ -22,9 +22,6 @@ library (sram_2_16_1_scn4m_subm_TT_5p0V_25C_lib){ slew_lower_threshold_pct_rise : 10.0 ; slew_upper_threshold_pct_rise : 90.0 ; - nom_voltage : 5.0; - nom_temperature : 25; - nom_process : 1.0; default_cell_leakage_power : 0.0 ; default_leakage_power_density : 0.0 ; default_input_pin_cap : 1.0 ; diff --git a/compiler/tests/golden/sram_2_16_1_scn4m_subm_TT_5p0V_25C_pruned.lib b/compiler/tests/golden/sram_2_16_1_scn4m_subm_TT_5p0V_25C_pruned.lib index 7b649d0d..0616f75e 100644 --- a/compiler/tests/golden/sram_2_16_1_scn4m_subm_TT_5p0V_25C_pruned.lib +++ b/compiler/tests/golden/sram_2_16_1_scn4m_subm_TT_5p0V_25C_pruned.lib @@ -22,9 +22,6 @@ library (sram_2_16_1_scn4m_subm_TT_5p0V_25C_lib){ slew_lower_threshold_pct_rise : 10.0 ; slew_upper_threshold_pct_rise : 90.0 ; - nom_voltage : 5.0; - nom_temperature : 25; - nom_process : 1.0; default_cell_leakage_power : 0.0 ; default_leakage_power_density : 0.0 ; default_input_pin_cap : 1.0 ; From d1b240dfb5859bf5710e60b4d37d100201672f3f Mon Sep 17 00:00:00 2001 From: Hunter Nichols Date: Thu, 21 Jan 2021 13:52:55 -0800 Subject: [PATCH 3/7] Added nom_voltage, etc back but changed values to replicate the operating conditions. Readded nom values back in golden files. --- compiler/characterizer/lib.py | 3 +++ .../golden/sram_2_16_1_freepdk45_FF_1p0V_25C_analytical.lib | 3 +++ .../golden/sram_2_16_1_freepdk45_SS_1p0V_25C_analytical.lib | 3 +++ compiler/tests/golden/sram_2_16_1_freepdk45_TT_1p0V_25C.lib | 3 +++ .../golden/sram_2_16_1_freepdk45_TT_1p0V_25C_analytical.lib | 3 +++ .../tests/golden/sram_2_16_1_freepdk45_TT_1p0V_25C_pruned.lib | 3 +++ .../golden/sram_2_16_1_scn4m_subm_FF_5p0V_25C_analytical.lib | 3 +++ .../golden/sram_2_16_1_scn4m_subm_SS_5p0V_25C_analytical.lib | 3 +++ compiler/tests/golden/sram_2_16_1_scn4m_subm_TT_5p0V_25C.lib | 3 +++ .../golden/sram_2_16_1_scn4m_subm_TT_5p0V_25C_analytical.lib | 3 +++ .../tests/golden/sram_2_16_1_scn4m_subm_TT_5p0V_25C_pruned.lib | 3 +++ 11 files changed, 33 insertions(+) diff --git a/compiler/characterizer/lib.py b/compiler/characterizer/lib.py index 9040f2e3..05db4147 100644 --- a/compiler/characterizer/lib.py +++ b/compiler/characterizer/lib.py @@ -224,6 +224,9 @@ class lib: self.lib.write(" slew_lower_threshold_pct_rise : 10.0 ;\n") self.lib.write(" slew_upper_threshold_pct_rise : 90.0 ;\n\n") + self.lib.write(" nom_voltage : {};\n".format(self.voltage)) + self.lib.write(" nom_temperature : {};\n".format(self.temperature)) + self.lib.write(" nom_process : 1.0;\n") self.lib.write(" default_cell_leakage_power : 0.0 ;\n") self.lib.write(" default_leakage_power_density : 0.0 ;\n") self.lib.write(" default_input_pin_cap : 1.0 ;\n") diff --git a/compiler/tests/golden/sram_2_16_1_freepdk45_FF_1p0V_25C_analytical.lib b/compiler/tests/golden/sram_2_16_1_freepdk45_FF_1p0V_25C_analytical.lib index 6ba1e114..b3ef0e0a 100644 --- a/compiler/tests/golden/sram_2_16_1_freepdk45_FF_1p0V_25C_analytical.lib +++ b/compiler/tests/golden/sram_2_16_1_freepdk45_FF_1p0V_25C_analytical.lib @@ -22,6 +22,9 @@ library (sram_2_16_1_freepdk45_FF_1p0V_25C_lib){ slew_lower_threshold_pct_rise : 10.0 ; slew_upper_threshold_pct_rise : 90.0 ; + nom_voltage : 1.0; + nom_temperature : 25; + nom_process : 1.0; default_cell_leakage_power : 0.0 ; default_leakage_power_density : 0.0 ; default_input_pin_cap : 1.0 ; diff --git a/compiler/tests/golden/sram_2_16_1_freepdk45_SS_1p0V_25C_analytical.lib b/compiler/tests/golden/sram_2_16_1_freepdk45_SS_1p0V_25C_analytical.lib index 2bde8e2b..34be4fe4 100644 --- a/compiler/tests/golden/sram_2_16_1_freepdk45_SS_1p0V_25C_analytical.lib +++ b/compiler/tests/golden/sram_2_16_1_freepdk45_SS_1p0V_25C_analytical.lib @@ -22,6 +22,9 @@ library (sram_2_16_1_freepdk45_SS_1p0V_25C_lib){ slew_lower_threshold_pct_rise : 10.0 ; slew_upper_threshold_pct_rise : 90.0 ; + nom_voltage : 1.0; + nom_temperature : 25; + nom_process : 1.0; default_cell_leakage_power : 0.0 ; default_leakage_power_density : 0.0 ; default_input_pin_cap : 1.0 ; diff --git a/compiler/tests/golden/sram_2_16_1_freepdk45_TT_1p0V_25C.lib b/compiler/tests/golden/sram_2_16_1_freepdk45_TT_1p0V_25C.lib index 82231d5d..cca9c1ed 100644 --- a/compiler/tests/golden/sram_2_16_1_freepdk45_TT_1p0V_25C.lib +++ b/compiler/tests/golden/sram_2_16_1_freepdk45_TT_1p0V_25C.lib @@ -22,6 +22,9 @@ library (sram_2_16_1_freepdk45_TT_1p0V_25C_lib){ slew_lower_threshold_pct_rise : 10.0 ; slew_upper_threshold_pct_rise : 90.0 ; + nom_voltage : 1.0; + nom_temperature : 25; + nom_process : 1.0; default_cell_leakage_power : 0.0 ; default_leakage_power_density : 0.0 ; default_input_pin_cap : 1.0 ; diff --git a/compiler/tests/golden/sram_2_16_1_freepdk45_TT_1p0V_25C_analytical.lib b/compiler/tests/golden/sram_2_16_1_freepdk45_TT_1p0V_25C_analytical.lib index 3f79ce08..26028892 100644 --- a/compiler/tests/golden/sram_2_16_1_freepdk45_TT_1p0V_25C_analytical.lib +++ b/compiler/tests/golden/sram_2_16_1_freepdk45_TT_1p0V_25C_analytical.lib @@ -22,6 +22,9 @@ library (sram_2_16_1_freepdk45_TT_1p0V_25C_lib){ slew_lower_threshold_pct_rise : 10.0 ; slew_upper_threshold_pct_rise : 90.0 ; + nom_voltage : 1.0; + nom_temperature : 25; + nom_process : 1.0; default_cell_leakage_power : 0.0 ; default_leakage_power_density : 0.0 ; default_input_pin_cap : 1.0 ; diff --git a/compiler/tests/golden/sram_2_16_1_freepdk45_TT_1p0V_25C_pruned.lib b/compiler/tests/golden/sram_2_16_1_freepdk45_TT_1p0V_25C_pruned.lib index bdaeab71..5817211b 100644 --- a/compiler/tests/golden/sram_2_16_1_freepdk45_TT_1p0V_25C_pruned.lib +++ b/compiler/tests/golden/sram_2_16_1_freepdk45_TT_1p0V_25C_pruned.lib @@ -22,6 +22,9 @@ library (sram_2_16_1_freepdk45_TT_1p0V_25C_lib){ slew_lower_threshold_pct_rise : 10.0 ; slew_upper_threshold_pct_rise : 90.0 ; + nom_voltage : 1.0; + nom_temperature : 25; + nom_process : 1.0; default_cell_leakage_power : 0.0 ; default_leakage_power_density : 0.0 ; default_input_pin_cap : 1.0 ; diff --git a/compiler/tests/golden/sram_2_16_1_scn4m_subm_FF_5p0V_25C_analytical.lib b/compiler/tests/golden/sram_2_16_1_scn4m_subm_FF_5p0V_25C_analytical.lib index c9d811b4..6912aec7 100644 --- a/compiler/tests/golden/sram_2_16_1_scn4m_subm_FF_5p0V_25C_analytical.lib +++ b/compiler/tests/golden/sram_2_16_1_scn4m_subm_FF_5p0V_25C_analytical.lib @@ -22,6 +22,9 @@ library (sram_2_16_1_scn4m_subm_FF_5p0V_25C_lib){ slew_lower_threshold_pct_rise : 10.0 ; slew_upper_threshold_pct_rise : 90.0 ; + nom_voltage : 5.0; + nom_temperature : 25; + nom_process : 1.0; default_cell_leakage_power : 0.0 ; default_leakage_power_density : 0.0 ; default_input_pin_cap : 1.0 ; diff --git a/compiler/tests/golden/sram_2_16_1_scn4m_subm_SS_5p0V_25C_analytical.lib b/compiler/tests/golden/sram_2_16_1_scn4m_subm_SS_5p0V_25C_analytical.lib index 605f88cc..a7605cb3 100644 --- a/compiler/tests/golden/sram_2_16_1_scn4m_subm_SS_5p0V_25C_analytical.lib +++ b/compiler/tests/golden/sram_2_16_1_scn4m_subm_SS_5p0V_25C_analytical.lib @@ -22,6 +22,9 @@ library (sram_2_16_1_scn4m_subm_SS_5p0V_25C_lib){ slew_lower_threshold_pct_rise : 10.0 ; slew_upper_threshold_pct_rise : 90.0 ; + nom_voltage : 5.0; + nom_temperature : 25; + nom_process : 1.0; default_cell_leakage_power : 0.0 ; default_leakage_power_density : 0.0 ; default_input_pin_cap : 1.0 ; diff --git a/compiler/tests/golden/sram_2_16_1_scn4m_subm_TT_5p0V_25C.lib b/compiler/tests/golden/sram_2_16_1_scn4m_subm_TT_5p0V_25C.lib index b416f3b5..8bec74c3 100644 --- a/compiler/tests/golden/sram_2_16_1_scn4m_subm_TT_5p0V_25C.lib +++ b/compiler/tests/golden/sram_2_16_1_scn4m_subm_TT_5p0V_25C.lib @@ -22,6 +22,9 @@ library (sram_2_16_1_scn4m_subm_TT_5p0V_25C_lib){ slew_lower_threshold_pct_rise : 10.0 ; slew_upper_threshold_pct_rise : 90.0 ; + nom_voltage : 5.0; + nom_temperature : 25; + nom_process : 1.0; default_cell_leakage_power : 0.0 ; default_leakage_power_density : 0.0 ; default_input_pin_cap : 1.0 ; diff --git a/compiler/tests/golden/sram_2_16_1_scn4m_subm_TT_5p0V_25C_analytical.lib b/compiler/tests/golden/sram_2_16_1_scn4m_subm_TT_5p0V_25C_analytical.lib index b416f3b5..8bec74c3 100644 --- a/compiler/tests/golden/sram_2_16_1_scn4m_subm_TT_5p0V_25C_analytical.lib +++ b/compiler/tests/golden/sram_2_16_1_scn4m_subm_TT_5p0V_25C_analytical.lib @@ -22,6 +22,9 @@ library (sram_2_16_1_scn4m_subm_TT_5p0V_25C_lib){ slew_lower_threshold_pct_rise : 10.0 ; slew_upper_threshold_pct_rise : 90.0 ; + nom_voltage : 5.0; + nom_temperature : 25; + nom_process : 1.0; default_cell_leakage_power : 0.0 ; default_leakage_power_density : 0.0 ; default_input_pin_cap : 1.0 ; diff --git a/compiler/tests/golden/sram_2_16_1_scn4m_subm_TT_5p0V_25C_pruned.lib b/compiler/tests/golden/sram_2_16_1_scn4m_subm_TT_5p0V_25C_pruned.lib index 0616f75e..7b649d0d 100644 --- a/compiler/tests/golden/sram_2_16_1_scn4m_subm_TT_5p0V_25C_pruned.lib +++ b/compiler/tests/golden/sram_2_16_1_scn4m_subm_TT_5p0V_25C_pruned.lib @@ -22,6 +22,9 @@ library (sram_2_16_1_scn4m_subm_TT_5p0V_25C_lib){ slew_lower_threshold_pct_rise : 10.0 ; slew_upper_threshold_pct_rise : 90.0 ; + nom_voltage : 5.0; + nom_temperature : 25; + nom_process : 1.0; default_cell_leakage_power : 0.0 ; default_leakage_power_density : 0.0 ; default_input_pin_cap : 1.0 ; From d354a847e611135b3b1914f5b7e5fbdd29714199 Mon Sep 17 00:00:00 2001 From: mrg Date: Sat, 13 Feb 2021 23:54:16 -0800 Subject: [PATCH 4/7] Remove gitlab badges. --- README.md | 4 ---- 1 file changed, 4 deletions(-) diff --git a/README.md b/README.md index dd7055e0..da68361b 100644 --- a/README.md +++ b/README.md @@ -4,13 +4,9 @@ [![License: BSD 3-clause](./images/license_badge.svg)](./LICENSE) Master: -[![Pipeline Status](https://scone.soe.ucsc.edu:8888/mrg/OpenRAM/badges/master/pipeline.svg)](https://github.com/VLSIDA/OpenRAM/commits/master) -![Coverage](https://scone.soe.ucsc.edu:8888/mrg/OpenRAM/badges/master/coverage.svg) [![Download](./images/download-stable-blue.svg)](https://github.com/VLSIDA/OpenRAM/archive/master.zip) Dev: -[![Pipeline Status](https://scone.soe.ucsc.edu:8888/mrg/OpenRAM/badges/dev/pipeline.svg)](https://github.com/VLSIDA/OpenRAM/commits/dev) -![Coverage](https://scone.soe.ucsc.edu:8888/mrg/OpenRAM/badges/dev/coverage.svg) [![Download](./images/download-unstable-blue.svg)](https://github.com/VLSIDA/OpenRAM/archive/dev.zip) An open-source static random access memory (SRAM) compiler. From 33bc9a597c12e9ae26d8e57dda620eae089e9e9c Mon Sep 17 00:00:00 2001 From: mrg Date: Mon, 15 Feb 2021 08:19:08 -0800 Subject: [PATCH 5/7] Remove dashes for Python module name warning. --- ...{riscv-freepdk45-8kbyte.py => riscv_freepdk45_8kbyte.py} | 0 ...m-16kbyte-1rw1r.py => riscv_scn4m_subm_16kbyte_1rw1r.py} | 0 ...ubm-1kbyte-1rw1r.py => riscv_scn4m_subm_1kbyte_1rw1r.py} | 0 ...bm-2kbyte-1rw1r.py => riscv_scn4m_subm_2skbyte_1rw1r.py} | 0 ...4m_subm-32kbyte.py => riscv_scn4m_subm_32kbyte_1rw1r.py} | 0 ...ubm-4kbyte-1rw1r.py => riscv_scn4m_subm_4kbyte_1rw1r.py} | 0 ...ubm-8kbyte-1rw1r.py => riscv_scn4m_subm_8kbyte_1rw1r.py} | 0 ...iscv-sky130-1kbyte-1rw.py => riscv_sky130_1kbyte_1rw.py} | 0 ...-sky130-1kbyte-1rw1r.py => riscv_sky130_1kbyte_1rw1r.py} | 6 +++--- ...iscv-sky130-2kbyte-1rw.py => riscv_sky130_2kbyte_1rw.py} | 0 ...-sky130-2kbyte-1rw1r.py => riscv_sky130_2kbyte_1rw1r.py} | 0 ...iscv-sky130-4kbyte-1rw.py => riscv_sky130_4kbyte_1rw.py} | 0 ...-sky130-4kbyte-1rw1r.py => riscv_sky130_4kbyte_1rw1r.py} | 0 13 files changed, 3 insertions(+), 3 deletions(-) rename compiler/example_configs/{riscv-freepdk45-8kbyte.py => riscv_freepdk45_8kbyte.py} (100%) rename compiler/example_configs/{riscv-scn4m_subm-16kbyte-1rw1r.py => riscv_scn4m_subm_16kbyte_1rw1r.py} (100%) rename compiler/example_configs/{riscv-scn4m_subm-1kbyte-1rw1r.py => riscv_scn4m_subm_1kbyte_1rw1r.py} (100%) rename compiler/example_configs/{riscv-scn4m_subm-2kbyte-1rw1r.py => riscv_scn4m_subm_2skbyte_1rw1r.py} (100%) rename compiler/example_configs/{riscv-scn4m_subm-32kbyte.py => riscv_scn4m_subm_32kbyte_1rw1r.py} (100%) rename compiler/example_configs/{riscv-scn4m_subm-4kbyte-1rw1r.py => riscv_scn4m_subm_4kbyte_1rw1r.py} (100%) rename compiler/example_configs/{riscv-scn4m_subm-8kbyte-1rw1r.py => riscv_scn4m_subm_8kbyte_1rw1r.py} (100%) rename compiler/example_configs/{riscv-sky130-1kbyte-1rw.py => riscv_sky130_1kbyte_1rw.py} (100%) rename compiler/example_configs/{riscv-sky130-1kbyte-1rw1r.py => riscv_sky130_1kbyte_1rw1r.py} (90%) rename compiler/example_configs/{riscv-sky130-2kbyte-1rw.py => riscv_sky130_2kbyte_1rw.py} (100%) rename compiler/example_configs/{riscv-sky130-2kbyte-1rw1r.py => riscv_sky130_2kbyte_1rw1r.py} (100%) rename compiler/example_configs/{riscv-sky130-4kbyte-1rw.py => riscv_sky130_4kbyte_1rw.py} (100%) rename compiler/example_configs/{riscv-sky130-4kbyte-1rw1r.py => riscv_sky130_4kbyte_1rw1r.py} (100%) diff --git a/compiler/example_configs/riscv-freepdk45-8kbyte.py b/compiler/example_configs/riscv_freepdk45_8kbyte.py similarity index 100% rename from compiler/example_configs/riscv-freepdk45-8kbyte.py rename to compiler/example_configs/riscv_freepdk45_8kbyte.py diff --git a/compiler/example_configs/riscv-scn4m_subm-16kbyte-1rw1r.py b/compiler/example_configs/riscv_scn4m_subm_16kbyte_1rw1r.py similarity index 100% rename from compiler/example_configs/riscv-scn4m_subm-16kbyte-1rw1r.py rename to compiler/example_configs/riscv_scn4m_subm_16kbyte_1rw1r.py diff --git a/compiler/example_configs/riscv-scn4m_subm-1kbyte-1rw1r.py b/compiler/example_configs/riscv_scn4m_subm_1kbyte_1rw1r.py similarity index 100% rename from compiler/example_configs/riscv-scn4m_subm-1kbyte-1rw1r.py rename to compiler/example_configs/riscv_scn4m_subm_1kbyte_1rw1r.py diff --git a/compiler/example_configs/riscv-scn4m_subm-2kbyte-1rw1r.py b/compiler/example_configs/riscv_scn4m_subm_2skbyte_1rw1r.py similarity index 100% rename from compiler/example_configs/riscv-scn4m_subm-2kbyte-1rw1r.py rename to compiler/example_configs/riscv_scn4m_subm_2skbyte_1rw1r.py diff --git a/compiler/example_configs/riscv-scn4m_subm-32kbyte.py b/compiler/example_configs/riscv_scn4m_subm_32kbyte_1rw1r.py similarity index 100% rename from compiler/example_configs/riscv-scn4m_subm-32kbyte.py rename to compiler/example_configs/riscv_scn4m_subm_32kbyte_1rw1r.py diff --git a/compiler/example_configs/riscv-scn4m_subm-4kbyte-1rw1r.py b/compiler/example_configs/riscv_scn4m_subm_4kbyte_1rw1r.py similarity index 100% rename from compiler/example_configs/riscv-scn4m_subm-4kbyte-1rw1r.py rename to compiler/example_configs/riscv_scn4m_subm_4kbyte_1rw1r.py diff --git a/compiler/example_configs/riscv-scn4m_subm-8kbyte-1rw1r.py b/compiler/example_configs/riscv_scn4m_subm_8kbyte_1rw1r.py similarity index 100% rename from compiler/example_configs/riscv-scn4m_subm-8kbyte-1rw1r.py rename to compiler/example_configs/riscv_scn4m_subm_8kbyte_1rw1r.py diff --git a/compiler/example_configs/riscv-sky130-1kbyte-1rw.py b/compiler/example_configs/riscv_sky130_1kbyte_1rw.py similarity index 100% rename from compiler/example_configs/riscv-sky130-1kbyte-1rw.py rename to compiler/example_configs/riscv_sky130_1kbyte_1rw.py diff --git a/compiler/example_configs/riscv-sky130-1kbyte-1rw1r.py b/compiler/example_configs/riscv_sky130_1kbyte_1rw1r.py similarity index 90% rename from compiler/example_configs/riscv-sky130-1kbyte-1rw1r.py rename to compiler/example_configs/riscv_sky130_1kbyte_1rw1r.py index 20463a99..d0b47857 100644 --- a/compiler/example_configs/riscv-sky130-1kbyte-1rw1r.py +++ b/compiler/example_configs/riscv_sky130_1kbyte_1rw1r.py @@ -2,7 +2,7 @@ word_size = 32 num_words = 256 write_size = 8 -local_array_size = 16 +#local_array_size = 16 num_rw_ports = 1 num_r_ports = 1 @@ -11,9 +11,9 @@ num_w_ports = 0 tech_name = "sky130" nominal_corner_only = True -route_supplies = False +#route_supplies = False check_lvsdrc = True -perimeter_pins = False +#perimeter_pins = False #netlist_only = True #analytical_delay = False output_name = "sram_{0}rw{1}r{2}w_{3}_{4}_{5}".format(num_rw_ports, diff --git a/compiler/example_configs/riscv-sky130-2kbyte-1rw.py b/compiler/example_configs/riscv_sky130_2kbyte_1rw.py similarity index 100% rename from compiler/example_configs/riscv-sky130-2kbyte-1rw.py rename to compiler/example_configs/riscv_sky130_2kbyte_1rw.py diff --git a/compiler/example_configs/riscv-sky130-2kbyte-1rw1r.py b/compiler/example_configs/riscv_sky130_2kbyte_1rw1r.py similarity index 100% rename from compiler/example_configs/riscv-sky130-2kbyte-1rw1r.py rename to compiler/example_configs/riscv_sky130_2kbyte_1rw1r.py diff --git a/compiler/example_configs/riscv-sky130-4kbyte-1rw.py b/compiler/example_configs/riscv_sky130_4kbyte_1rw.py similarity index 100% rename from compiler/example_configs/riscv-sky130-4kbyte-1rw.py rename to compiler/example_configs/riscv_sky130_4kbyte_1rw.py diff --git a/compiler/example_configs/riscv-sky130-4kbyte-1rw1r.py b/compiler/example_configs/riscv_sky130_4kbyte_1rw1r.py similarity index 100% rename from compiler/example_configs/riscv-sky130-4kbyte-1rw1r.py rename to compiler/example_configs/riscv_sky130_4kbyte_1rw1r.py From f5c86f70a3843dd73ed2b65b27f038cefe61c5b3 Mon Sep 17 00:00:00 2001 From: mrg Date: Mon, 15 Feb 2021 08:19:37 -0800 Subject: [PATCH 6/7] Change to 32 threads --- .github/workflows/ci.yml | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/.github/workflows/ci.yml b/.github/workflows/ci.yml index 2df69733..00b23115 100644 --- a/.github/workflows/ci.yml +++ b/.github/workflows/ci.yml @@ -12,7 +12,7 @@ jobs: export OPENRAM_HOME="`pwd`/compiler" export OPENRAM_TECH="`pwd`/technology:/software/PDKs/skywater-tech" export OPENRAM_TMP="`pwd`/scn4me_subm" - python3-coverage run -p $OPENRAM_HOME/tests/regress.py -j 20 -t scn4m_subm + python3-coverage run -p $OPENRAM_HOME/tests/regress.py -j 32 -t scn4m_subm - name: Archive if: ${{ failure() }} uses: actions/upload-artifact@v2 @@ -30,7 +30,7 @@ jobs: export OPENRAM_HOME="`pwd`/compiler" export OPENRAM_TECH="`pwd`/technology:/software/PDKs/skywater-tech" export OPENRAM_TMP="`pwd`/freepdk45" - python3-coverage run -p $OPENRAM_HOME/tests/regress.py -j 20 -t freepdk45 + python3-coverage run -p $OPENRAM_HOME/tests/regress.py -j 32 -t freepdk45 - name: Archive if: ${{ failure() }} uses: actions/upload-artifact@v2 From c3156be7b1bdecbb37310634034847ffdfcb6025 Mon Sep 17 00:00:00 2001 From: mrg Date: Mon, 15 Feb 2021 12:02:22 -0800 Subject: [PATCH 7/7] Change from 32 to 48 threads --- .github/workflows/ci.yml | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/.github/workflows/ci.yml b/.github/workflows/ci.yml index 00b23115..6a7cd73b 100644 --- a/.github/workflows/ci.yml +++ b/.github/workflows/ci.yml @@ -12,7 +12,7 @@ jobs: export OPENRAM_HOME="`pwd`/compiler" export OPENRAM_TECH="`pwd`/technology:/software/PDKs/skywater-tech" export OPENRAM_TMP="`pwd`/scn4me_subm" - python3-coverage run -p $OPENRAM_HOME/tests/regress.py -j 32 -t scn4m_subm + python3-coverage run -p $OPENRAM_HOME/tests/regress.py -j 48 -t scn4m_subm - name: Archive if: ${{ failure() }} uses: actions/upload-artifact@v2 @@ -30,7 +30,7 @@ jobs: export OPENRAM_HOME="`pwd`/compiler" export OPENRAM_TECH="`pwd`/technology:/software/PDKs/skywater-tech" export OPENRAM_TMP="`pwd`/freepdk45" - python3-coverage run -p $OPENRAM_HOME/tests/regress.py -j 32 -t freepdk45 + python3-coverage run -p $OPENRAM_HOME/tests/regress.py -j 48 -t freepdk45 - name: Archive if: ${{ failure() }} uses: actions/upload-artifact@v2