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Undo delay changes. Fix bus order for DRC.

This commit is contained in:
Matt Guthaus 2019-08-06 17:17:59 -07:00
parent a2f81aeae4
commit ae46a464b9
2 changed files with 6 additions and 6 deletions
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6
compiler/modules/bank.py
View File

@ -304,13 +304,13 @@ class bank(design.design):
self.input_control_signals = [] self.input_control_signals = []
port_num = 0 port_num = 0
for port in range(OPTS.num_rw_ports): for port in range(OPTS.num_rw_ports):
self.input_control_signals.append(["wl_en{}".format(port_num), "w_en{}".format(port_num), "s_en{}".format(port_num), "p_en_bar{}".format(port_num)]) self.input_control_signals.append(["w_en{}".format(port_num), "s_en{}".format(port_num), "p_en_bar{}".format(port_num), "wl_en{}".format(port_num)])
port_num += 1 port_num += 1
for port in range(OPTS.num_w_ports): for port in range(OPTS.num_w_ports):
self.input_control_signals.append(["wl_en{}".format(port_num), "w_en{}".format(port_num), "p_en_bar{}".format(port_num)]) self.input_control_signals.append(["w_en{}".format(port_num), "p_en_bar{}".format(port_num), "wl_en{}".format(port_num)])
port_num += 1 port_num += 1
for port in range(OPTS.num_r_ports): for port in range(OPTS.num_r_ports):
self.input_control_signals.append(["wl_en{}".format(port_num), "s_en{}".format(port_num), "p_en_bar{}".format(port_num)]) self.input_control_signals.append(["s_en{}".format(port_num), "p_en_bar{}".format(port_num), "wl_en{}".format(port_num)])
port_num += 1 port_num += 1
# Number of control lines in the bus for each port # Number of control lines in the bus for each port

6
compiler/modules/control_logic.py
View File

@ -120,7 +120,7 @@ class control_logic(design.design):
# wl_en drives every row in the bank # wl_en drives every row in the bank
self.wl_en_driver = factory.create(module_type="pdriver", self.wl_en_driver = factory.create(module_type="pdriver",
fanout=max_fanout, fanout=self.num_rows,
height=dff_height) height=dff_height)
self.add_mod(self.wl_en_driver) self.add_mod(self.wl_en_driver)
@ -145,9 +145,9 @@ class control_logic(design.design):
# p_en_bar drives every column in the bitcell array # p_en_bar drives every column in the bitcell array
# but it is sized the same as the wl_en driver with # but it is sized the same as the wl_en driver with
# prepended 3 inverter stages to guarantee it is slower and odd polarity # prepended 3 inverter stages to guarantee it is slower and odd polarity
driver_size_list = [1,1,1,*self.wl_en_driver.get_sizes()]
self.p_en_bar_driver = factory.create(module_type="pdriver", self.p_en_bar_driver = factory.create(module_type="pdriver",
size_list=driver_size_list, fanout=self.num_cols,
neg_polarity=True,
height=dff_height) height=dff_height)
self.add_mod(self.p_en_bar_driver) self.add_mod(self.p_en_bar_driver)