diff --git a/compiler/modules/bank.py b/compiler/modules/bank.py
index f3491b79..4fa95c44 100644
--- a/compiler/modules/bank.py
+++ b/compiler/modules/bank.py
@@ -304,13 +304,13 @@ class bank(design.design):
         self.input_control_signals = []
         port_num = 0
         for port in range(OPTS.num_rw_ports):
-            self.input_control_signals.append(["wl_en{}".format(port_num), "w_en{}".format(port_num), "s_en{}".format(port_num), "p_en_bar{}".format(port_num)])
+            self.input_control_signals.append(["w_en{}".format(port_num), "s_en{}".format(port_num), "p_en_bar{}".format(port_num), "wl_en{}".format(port_num)])
             port_num += 1
         for port in range(OPTS.num_w_ports):
-            self.input_control_signals.append(["wl_en{}".format(port_num), "w_en{}".format(port_num), "p_en_bar{}".format(port_num)])
+            self.input_control_signals.append(["w_en{}".format(port_num), "p_en_bar{}".format(port_num), "wl_en{}".format(port_num)])
             port_num += 1
         for port in range(OPTS.num_r_ports):
-            self.input_control_signals.append(["wl_en{}".format(port_num), "s_en{}".format(port_num), "p_en_bar{}".format(port_num)])
+            self.input_control_signals.append(["s_en{}".format(port_num), "p_en_bar{}".format(port_num), "wl_en{}".format(port_num)])
             port_num += 1
 
         # Number of control lines in the bus for each port
diff --git a/compiler/modules/control_logic.py b/compiler/modules/control_logic.py
index f5531d6f..a5c5dc12 100644
--- a/compiler/modules/control_logic.py
+++ b/compiler/modules/control_logic.py
@@ -120,7 +120,7 @@ class control_logic(design.design):
         
         # wl_en drives every row in the bank
         self.wl_en_driver = factory.create(module_type="pdriver",
-                                           fanout=max_fanout,
+                                           fanout=self.num_rows,
                                            height=dff_height)
         self.add_mod(self.wl_en_driver)
 
@@ -145,9 +145,9 @@ class control_logic(design.design):
         # p_en_bar drives every column in the bitcell array
         # but it is sized the same as the wl_en driver with
         # prepended 3 inverter stages to guarantee it is slower and odd polarity
-        driver_size_list = [1,1,1,*self.wl_en_driver.get_sizes()]
         self.p_en_bar_driver = factory.create(module_type="pdriver",
-                                              size_list=driver_size_list,
+                                              fanout=self.num_cols,
+                                              neg_polarity=True,
                                               height=dff_height)
         self.add_mod(self.p_en_bar_driver)