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Add direction to pins of all modules

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This commit is contained in:
Matt Guthaus
2019-08-06 14:14:09 -07:00
parent c3f38a5cac
commit ad35f8745e
22 changed files with 109 additions and 104 deletions
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compiler/modules/bitcell_array.py
+4 -4
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@@ -77,12 +77,12 @@ class bitcell_array(design.design):
column_list = self.cell.get_all_bitline_names()
for col in range(self.column_size):
for cell_column in column_list:
self.add_pin(cell_column+"_{0}".format(col))
self.add_pin(cell_column+"_{0}".format(col), "INOUT")
for row in range(self.row_size):
for cell_row in row_list:
self.add_pin(cell_row+"_{0}".format(row))
self.add_pin("vdd")
self.add_pin("gnd")
self.add_pin(cell_row+"_{0}".format(row), "INPUT")
self.add_pin("vdd", "POWER")
self.add_pin("gnd", "GROUND")
def add_modules(self):
""" Add the modules used in this design """
compiler/modules/delay_chain.py
+4 -4
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@@ -57,10 +57,10 @@ class delay_chain(design.design):
def add_pins(self):
""" Add the pins of the delay chain"""
self.add_pin("in")
self.add_pin("out")
self.add_pin("vdd")
self.add_pin("gnd")
self.add_pin("in", "INPUT")
self.add_pin("out", "OUTPUT")
self.add_pin("vdd", "POWER")
self.add_pin("gnd", "GROUND")
def add_modules(self):
self.inv = factory.create(module_type="pinv", route_output=False)
compiler/modules/dff_array.py
+5 -5
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@@ -54,13 +54,13 @@ class dff_array(design.design):
def add_pins(self):
for row in range(self.rows):
for col in range(self.columns):
self.add_pin(self.get_din_name(row,col))
self.add_pin(self.get_din_name(row,col), "INPUT")
for row in range(self.rows):
for col in range(self.columns):
self.add_pin(self.get_dout_name(row,col))
self.add_pin("clk")
self.add_pin("vdd")
self.add_pin("gnd")
self.add_pin(self.get_dout_name(row,col), "OUTPUT")
self.add_pin("clk", "INPUT")
self.add_pin("vdd", "POWER")
self.add_pin("gnd", "GROUND")
def create_dff_array(self):
self.dff_insts={}
compiler/modules/dff_buf.py
+6 -6
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@@ -75,12 +75,12 @@ class dff_buf(design.design):
def add_pins(self):
self.add_pin("D")
self.add_pin("Q")
self.add_pin("Qb")
self.add_pin("clk")
self.add_pin("vdd")
self.add_pin("gnd")
self.add_pin("D", "INPUT")
self.add_pin("Q", "OUTPUT")
self.add_pin("Qb", "OUTPUT")
self.add_pin("clk", "INPUT")
self.add_pin("vdd", "POWER")
self.add_pin("gnd", "GROUND")
def create_instances(self):
self.dff_inst=self.add_inst(name="dff_buf_dff",
compiler/modules/dff_buf_array.py
+6 -6
View File
@@ -55,14 +55,14 @@ class dff_buf_array(design.design):
def add_pins(self):
for row in range(self.rows):
for col in range(self.columns):
self.add_pin(self.get_din_name(row,col))
self.add_pin(self.get_din_name(row,col), "INPUT")
for row in range(self.rows):
for col in range(self.columns):
self.add_pin(self.get_dout_name(row,col))
self.add_pin(self.get_dout_bar_name(row,col))
self.add_pin("clk")
self.add_pin("vdd")
self.add_pin("gnd")
self.add_pin(self.get_dout_name(row,col), "OUTPUT")
self.add_pin(self.get_dout_bar_name(row,col), "OUTPUT")
self.add_pin("clk", "INPUT")
self.add_pin("vdd", "POWER")
self.add_pin("gnd", "GROUND")
def add_modules(self):
self.dff = factory.create(module_type="dff_buf",
compiler/modules/dff_inv_array.py
+6 -6
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@@ -59,14 +59,14 @@ class dff_inv_array(design.design):
def add_pins(self):
for row in range(self.rows):
for col in range(self.columns):
self.add_pin(self.get_din_name(row,col))
self.add_pin(self.get_din_name(row,col), "INPUT")
for row in range(self.rows):
for col in range(self.columns):
self.add_pin(self.get_dout_name(row,col))
self.add_pin(self.get_dout_bar_name(row,col))
self.add_pin("clk")
self.add_pin("vdd")
self.add_pin("gnd")
self.add_pin(self.get_dout_name(row,col), "OUTPUT")
self.add_pin(self.get_dout_bar_name(row,col), "OUTPUT")
self.add_pin("clk", "INPUT")
self.add_pin("vdd", "POWER")
self.add_pin("gnd", "GROUND")
def create_dff_array(self):
self.dff_insts={}
compiler/modules/dummy_array.py
+4 -4
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@@ -70,12 +70,12 @@ class dummy_array(design.design):
column_list = self.cell.get_all_bitline_names()
for col in range(self.column_size):
for cell_column in column_list:
self.add_pin(cell_column+"_{0}".format(col))
self.add_pin(cell_column+"_{0}".format(col), "INOUT")
for row in range(self.row_size):
for cell_row in row_list:
self.add_pin(cell_row+"_{0}".format(row))
self.add_pin("vdd")
self.add_pin("gnd")
self.add_pin(cell_row+"_{0}".format(row), "INPUT")
self.add_pin("vdd", "POWER")
self.add_pin("gnd", "GROUND")
def add_modules(self):
""" Add the modules used in this design """
compiler/modules/hierarchical_decoder.py
+4 -4
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@@ -231,12 +231,12 @@ class hierarchical_decoder(design.design):
""" Add the module pins """
for i in range(self.num_inputs):
self.add_pin("addr_{0}".format(i))
self.add_pin("addr_{0}".format(i), "INPUT")
for j in range(self.rows):
self.add_pin("decode_{0}".format(j))
self.add_pin("vdd")
self.add_pin("gnd")
self.add_pin("decode_{0}".format(j), "OUTPUT")
self.add_pin("vdd", "POWER")
self.add_pin("gnd", "GROUND")
def create_pre_decoder(self):
compiler/modules/hierarchical_predecode.py
+4 -4
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@@ -26,11 +26,11 @@ class hierarchical_predecode(design.design):
def add_pins(self):
for k in range(self.number_of_inputs):
self.add_pin("in_{0}".format(k))
self.add_pin("in_{0}".format(k), "INPUT")
for i in range(self.number_of_outputs):
self.add_pin("out_{0}".format(i))
self.add_pin("vdd")
self.add_pin("gnd")
self.add_pin("out_{0}".format(i), "OUTPUT")
self.add_pin("vdd", "POWER")
self.add_pin("gnd", "GROUND")
def add_modules(self):
""" Add the INV and NAND gate modules """
compiler/modules/precharge_array.py
+6 -5
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@@ -35,10 +35,11 @@ class precharge_array(design.design):
def add_pins(self):
"""Adds pins for spice file"""
for i in range(self.columns):
self.add_pin("bl_{0}".format(i))
self.add_pin("br_{0}".format(i))
self.add_pin("en_bar")
self.add_pin("vdd")
# These are outputs from the precharge only
self.add_pin("bl_{0}".format(i), "OUTPUT")
self.add_pin("br_{0}".format(i), "OUTPUT")
self.add_pin("en_bar", "INPUT")
self.add_pin("vdd", "POWER")
def create_netlist(self):
self.add_modules()
@@ -115,4 +116,4 @@ class precharge_array(design.design):
#Assume single port
precharge_en_cin = self.pc_cell.get_en_cin()
return precharge_en_cin*self.columns
compiler/modules/replica_column.py
+5 -4
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@@ -55,14 +55,15 @@ class replica_column(design.design):
def add_pins(self):
for bl_name in self.cell.get_all_bitline_names():
self.add_pin("{0}_{1}".format(bl_name,0))
# In the replica column, these are only outputs!
self.add_pin("{0}_{1}".format(bl_name,0), "OUTPUT")
for row in range(self.total_size):
for wl_name in self.cell.get_all_wl_names():
self.add_pin("{0}_{1}".format(wl_name,row))
self.add_pin("{0}_{1}".format(wl_name,row), "INPUT")
self.add_pin("vdd")
self.add_pin("gnd")
self.add_pin("vdd", "POWER")
self.add_pin("gnd", "GROUND")
def add_modules(self):
self.replica_cell = factory.create(module_type="replica_bitcell")
compiler/modules/sense_amp_array.py
+6 -6
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@@ -55,12 +55,12 @@ class sense_amp_array(design.design):
def add_pins(self):
for i in range(0,self.word_size):
self.add_pin("data_{0}".format(i))
self.add_pin("bl_{0}".format(i))
self.add_pin("br_{0}".format(i))
self.add_pin("en")
self.add_pin("vdd")
self.add_pin("gnd")
self.add_pin("data_{0}".format(i), "OUTPUT")
self.add_pin("bl_{0}".format(i), "INPUT")
self.add_pin("br_{0}".format(i), "INPUT")
self.add_pin("en", "INPUT")
self.add_pin("vdd", "POWER")
self.add_pin("gnd", "GROUND")
def add_modules(self):
self.amp = factory.create(module_type="sense_amp")
compiler/modules/wordline_driver.py
+5 -5
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@@ -50,13 +50,13 @@ class wordline_driver(design.design):
def add_pins(self):
# inputs to wordline_driver.
for i in range(self.rows):
self.add_pin("in_{0}".format(i))
self.add_pin("in_{0}".format(i), "INPUT")
# Outputs from wordline_driver.
for i in range(self.rows):
self.add_pin("wl_{0}".format(i))
self.add_pin("en")
self.add_pin("vdd")
self.add_pin("gnd")
self.add_pin("wl_{0}".format(i), "OUTPUT")
self.add_pin("en", "INPUT")
self.add_pin("vdd", "POWER")
self.add_pin("gnd", "GROUND")
def add_modules(self):
compiler/modules/write_driver_array.py
+7 -7
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@@ -59,17 +59,17 @@ class write_driver_array(design.design):
def add_pins(self):
for i in range(self.word_size):
self.add_pin("data_{0}".format(i))
self.add_pin("data_{0}".format(i), "INPUT")
for i in range(self.word_size):
self.add_pin("bl_{0}".format(i))
self.add_pin("br_{0}".format(i))
self.add_pin("bl_{0}".format(i), "OUTPUT")
self.add_pin("br_{0}".format(i), "OUTPUT")
if self.write_size != None:
for i in range(self.num_wmasks):
self.add_pin("en_{}".format(i))
self.add_pin("en_{}".format(i), "INPUT")
else:
self.add_pin("en")
self.add_pin("vdd")
self.add_pin("gnd")
self.add_pin("en", "INPUT")
self.add_pin("vdd", "POWER")
self.add_pin("gnd", "GROUND")
def add_modules(self):
self.driver = factory.create(module_type="write_driver")