From ad35f8745ee88499d9af51e9ce444f7622b4ee85 Mon Sep 17 00:00:00 2001
From: Matt Guthaus <mrg@ucsc.edu>
Date: Tue, 6 Aug 2019 14:14:09 -0700
Subject: [PATCH] Add direction to pins of all modules

---
 compiler/modules/bitcell_array.py          |  8 ++---
 compiler/modules/delay_chain.py            |  8 ++---
 compiler/modules/dff_array.py              | 10 +++----
 compiler/modules/dff_buf.py                | 12 ++++----
 compiler/modules/dff_buf_array.py          | 12 ++++----
 compiler/modules/dff_inv_array.py          | 12 ++++----
 compiler/modules/dummy_array.py            |  8 ++---
 compiler/modules/hierarchical_decoder.py   |  8 ++---
 compiler/modules/hierarchical_predecode.py |  8 ++---
 compiler/modules/precharge_array.py        | 11 +++----
 compiler/modules/replica_column.py         |  9 +++---
 compiler/modules/sense_amp_array.py        | 12 ++++----
 compiler/modules/wordline_driver.py        | 10 +++----
 compiler/modules/write_driver_array.py     | 14 ++++-----
 compiler/pgates/pand2.py                   | 10 +++----
 compiler/pgates/pbuf.py                    |  8 ++---
 compiler/pgates/pdriver.py                 | 35 ++++++++++++----------
 compiler/pgates/pinv.py                    |  4 +--
 compiler/pgates/pnand2.py                  |  4 +--
 compiler/pgates/pnand3.py                  |  4 +--
 compiler/pgates/pnor2.py                   |  4 +--
 compiler/pgates/precharge.py               |  2 +-
 22 files changed, 109 insertions(+), 104 deletions(-)

diff --git a/compiler/modules/bitcell_array.py b/compiler/modules/bitcell_array.py
index 4b8ac212..999382ec 100644
--- a/compiler/modules/bitcell_array.py
+++ b/compiler/modules/bitcell_array.py
@@ -77,12 +77,12 @@ class bitcell_array(design.design):
         column_list = self.cell.get_all_bitline_names()
         for col in range(self.column_size):
             for cell_column in column_list:
-                self.add_pin(cell_column+"_{0}".format(col))
+                self.add_pin(cell_column+"_{0}".format(col), "INOUT")
         for row in range(self.row_size):
             for cell_row in row_list:
-                    self.add_pin(cell_row+"_{0}".format(row))
-        self.add_pin("vdd")
-        self.add_pin("gnd")
+                    self.add_pin(cell_row+"_{0}".format(row), "INPUT")
+        self.add_pin("vdd", "POWER")
+        self.add_pin("gnd", "GROUND")
 
     def add_modules(self):
         """ Add the modules used in this design """
diff --git a/compiler/modules/delay_chain.py b/compiler/modules/delay_chain.py
index 6a54c1a3..bc932a26 100644
--- a/compiler/modules/delay_chain.py
+++ b/compiler/modules/delay_chain.py
@@ -57,10 +57,10 @@ class delay_chain(design.design):
         
     def add_pins(self):
         """ Add the pins of the delay chain"""
-        self.add_pin("in")
-        self.add_pin("out")
-        self.add_pin("vdd")
-        self.add_pin("gnd")
+        self.add_pin("in", "INPUT")
+        self.add_pin("out", "OUTPUT")
+        self.add_pin("vdd", "POWER")
+        self.add_pin("gnd", "GROUND")
 
     def add_modules(self):
         self.inv = factory.create(module_type="pinv", route_output=False)
diff --git a/compiler/modules/dff_array.py b/compiler/modules/dff_array.py
index 3ea3fc7f..32b36765 100644
--- a/compiler/modules/dff_array.py
+++ b/compiler/modules/dff_array.py
@@ -54,13 +54,13 @@ class dff_array(design.design):
     def add_pins(self):
         for row in range(self.rows):  
             for col in range(self.columns):
-                self.add_pin(self.get_din_name(row,col))
+                self.add_pin(self.get_din_name(row,col), "INPUT")
         for row in range(self.rows):  
             for col in range(self.columns):
-                self.add_pin(self.get_dout_name(row,col))
-        self.add_pin("clk")
-        self.add_pin("vdd")
-        self.add_pin("gnd")
+                self.add_pin(self.get_dout_name(row,col), "OUTPUT")
+        self.add_pin("clk", "INPUT")
+        self.add_pin("vdd", "POWER")
+        self.add_pin("gnd", "GROUND")
 
     def create_dff_array(self):
         self.dff_insts={}
diff --git a/compiler/modules/dff_buf.py b/compiler/modules/dff_buf.py
index 9533d647..9359329a 100644
--- a/compiler/modules/dff_buf.py
+++ b/compiler/modules/dff_buf.py
@@ -75,12 +75,12 @@ class dff_buf(design.design):
         
         
     def add_pins(self):
-        self.add_pin("D")
-        self.add_pin("Q")
-        self.add_pin("Qb")
-        self.add_pin("clk")
-        self.add_pin("vdd")
-        self.add_pin("gnd")
+        self.add_pin("D", "INPUT")
+        self.add_pin("Q", "OUTPUT")
+        self.add_pin("Qb", "OUTPUT")
+        self.add_pin("clk", "INPUT")
+        self.add_pin("vdd", "POWER")
+        self.add_pin("gnd", "GROUND")
 
     def create_instances(self):
         self.dff_inst=self.add_inst(name="dff_buf_dff",
diff --git a/compiler/modules/dff_buf_array.py b/compiler/modules/dff_buf_array.py
index 60bdae02..df36b2aa 100644
--- a/compiler/modules/dff_buf_array.py
+++ b/compiler/modules/dff_buf_array.py
@@ -55,14 +55,14 @@ class dff_buf_array(design.design):
     def add_pins(self):
         for row in range(self.rows):  
             for col in range(self.columns):
-                self.add_pin(self.get_din_name(row,col))
+                self.add_pin(self.get_din_name(row,col), "INPUT")
         for row in range(self.rows):  
             for col in range(self.columns):
-                self.add_pin(self.get_dout_name(row,col))
-                self.add_pin(self.get_dout_bar_name(row,col))
-        self.add_pin("clk")
-        self.add_pin("vdd")
-        self.add_pin("gnd")
+                self.add_pin(self.get_dout_name(row,col), "OUTPUT")
+                self.add_pin(self.get_dout_bar_name(row,col), "OUTPUT")
+        self.add_pin("clk", "INPUT")
+        self.add_pin("vdd", "POWER")
+        self.add_pin("gnd", "GROUND")
 
     def add_modules(self):
         self.dff = factory.create(module_type="dff_buf",
diff --git a/compiler/modules/dff_inv_array.py b/compiler/modules/dff_inv_array.py
index 1e6754b9..051dd237 100644
--- a/compiler/modules/dff_inv_array.py
+++ b/compiler/modules/dff_inv_array.py
@@ -59,14 +59,14 @@ class dff_inv_array(design.design):
     def add_pins(self):
         for row in range(self.rows):  
             for col in range(self.columns):
-                self.add_pin(self.get_din_name(row,col))
+                self.add_pin(self.get_din_name(row,col), "INPUT")
         for row in range(self.rows):  
             for col in range(self.columns):
-                self.add_pin(self.get_dout_name(row,col))
-                self.add_pin(self.get_dout_bar_name(row,col))
-        self.add_pin("clk")
-        self.add_pin("vdd")
-        self.add_pin("gnd")
+                self.add_pin(self.get_dout_name(row,col), "OUTPUT")
+                self.add_pin(self.get_dout_bar_name(row,col), "OUTPUT")
+        self.add_pin("clk", "INPUT")
+        self.add_pin("vdd", "POWER")
+        self.add_pin("gnd", "GROUND")
 
     def create_dff_array(self):
         self.dff_insts={}
diff --git a/compiler/modules/dummy_array.py b/compiler/modules/dummy_array.py
index 10007106..f1f433ce 100644
--- a/compiler/modules/dummy_array.py
+++ b/compiler/modules/dummy_array.py
@@ -70,12 +70,12 @@ class dummy_array(design.design):
         column_list = self.cell.get_all_bitline_names()
         for col in range(self.column_size):
             for cell_column in column_list:
-                self.add_pin(cell_column+"_{0}".format(col))
+                self.add_pin(cell_column+"_{0}".format(col), "INOUT")
         for row in range(self.row_size):
             for cell_row in row_list:
-                    self.add_pin(cell_row+"_{0}".format(row))
-        self.add_pin("vdd")
-        self.add_pin("gnd")
+                    self.add_pin(cell_row+"_{0}".format(row), "INPUT")
+        self.add_pin("vdd", "POWER")
+        self.add_pin("gnd", "GROUND")
 
     def add_modules(self):
         """ Add the modules used in this design """
diff --git a/compiler/modules/hierarchical_decoder.py b/compiler/modules/hierarchical_decoder.py
index 4f359c95..75eb3345 100644
--- a/compiler/modules/hierarchical_decoder.py
+++ b/compiler/modules/hierarchical_decoder.py
@@ -231,12 +231,12 @@ class hierarchical_decoder(design.design):
         """ Add the module pins """
         
         for i in range(self.num_inputs):
-            self.add_pin("addr_{0}".format(i))
+            self.add_pin("addr_{0}".format(i), "INPUT")
 
         for j in range(self.rows):
-            self.add_pin("decode_{0}".format(j))
-        self.add_pin("vdd")
-        self.add_pin("gnd")
+            self.add_pin("decode_{0}".format(j), "OUTPUT")
+        self.add_pin("vdd", "POWER")
+        self.add_pin("gnd", "GROUND")
 
 
     def create_pre_decoder(self):
diff --git a/compiler/modules/hierarchical_predecode.py b/compiler/modules/hierarchical_predecode.py
index a8d4797f..bec0ce06 100644
--- a/compiler/modules/hierarchical_predecode.py
+++ b/compiler/modules/hierarchical_predecode.py
@@ -26,11 +26,11 @@ class hierarchical_predecode(design.design):
     
     def add_pins(self):
         for k in range(self.number_of_inputs):
-            self.add_pin("in_{0}".format(k))
+            self.add_pin("in_{0}".format(k), "INPUT")
         for i in range(self.number_of_outputs):
-            self.add_pin("out_{0}".format(i))
-        self.add_pin("vdd")
-        self.add_pin("gnd")
+            self.add_pin("out_{0}".format(i), "OUTPUT")
+        self.add_pin("vdd", "POWER")
+        self.add_pin("gnd", "GROUND")
 
     def add_modules(self):
         """ Add the INV and NAND gate modules """
diff --git a/compiler/modules/precharge_array.py b/compiler/modules/precharge_array.py
index bf45afd5..2d98ba14 100644
--- a/compiler/modules/precharge_array.py
+++ b/compiler/modules/precharge_array.py
@@ -35,10 +35,11 @@ class precharge_array(design.design):
     def add_pins(self):
         """Adds pins for spice file"""
         for i in range(self.columns):
-            self.add_pin("bl_{0}".format(i))
-            self.add_pin("br_{0}".format(i))
-        self.add_pin("en_bar")
-        self.add_pin("vdd")
+            # These are outputs from the precharge only
+            self.add_pin("bl_{0}".format(i), "OUTPUT")
+            self.add_pin("br_{0}".format(i), "OUTPUT")
+        self.add_pin("en_bar", "INPUT")
+        self.add_pin("vdd", "POWER")
 
     def create_netlist(self):
         self.add_modules()
@@ -115,4 +116,4 @@ class precharge_array(design.design):
         #Assume single port
         precharge_en_cin = self.pc_cell.get_en_cin()
         return precharge_en_cin*self.columns  
-        
\ No newline at end of file
+        
diff --git a/compiler/modules/replica_column.py b/compiler/modules/replica_column.py
index fb11a8f5..c3f63b19 100644
--- a/compiler/modules/replica_column.py
+++ b/compiler/modules/replica_column.py
@@ -55,14 +55,15 @@ class replica_column(design.design):
     def add_pins(self):
         
         for bl_name in self.cell.get_all_bitline_names():
-            self.add_pin("{0}_{1}".format(bl_name,0))
+            # In the replica column, these are only outputs!
+            self.add_pin("{0}_{1}".format(bl_name,0), "OUTPUT")
 
         for row in range(self.total_size):
             for wl_name in self.cell.get_all_wl_names():
-                self.add_pin("{0}_{1}".format(wl_name,row))
+                self.add_pin("{0}_{1}".format(wl_name,row), "INPUT")
                     
-        self.add_pin("vdd")
-        self.add_pin("gnd")
+        self.add_pin("vdd", "POWER")
+        self.add_pin("gnd", "GROUND")
 
     def add_modules(self):
         self.replica_cell = factory.create(module_type="replica_bitcell")
diff --git a/compiler/modules/sense_amp_array.py b/compiler/modules/sense_amp_array.py
index ab67e981..40c3adeb 100644
--- a/compiler/modules/sense_amp_array.py
+++ b/compiler/modules/sense_amp_array.py
@@ -55,12 +55,12 @@ class sense_amp_array(design.design):
 
     def add_pins(self):
         for i in range(0,self.word_size):
-            self.add_pin("data_{0}".format(i))
-            self.add_pin("bl_{0}".format(i))
-            self.add_pin("br_{0}".format(i))
-        self.add_pin("en")
-        self.add_pin("vdd")
-        self.add_pin("gnd")
+            self.add_pin("data_{0}".format(i), "OUTPUT")
+            self.add_pin("bl_{0}".format(i), "INPUT")
+            self.add_pin("br_{0}".format(i), "INPUT")
+        self.add_pin("en", "INPUT")
+        self.add_pin("vdd", "POWER")
+        self.add_pin("gnd", "GROUND")
         
     def add_modules(self):
         self.amp = factory.create(module_type="sense_amp")
diff --git a/compiler/modules/wordline_driver.py b/compiler/modules/wordline_driver.py
index b29901c5..39700799 100644
--- a/compiler/modules/wordline_driver.py
+++ b/compiler/modules/wordline_driver.py
@@ -50,13 +50,13 @@ class wordline_driver(design.design):
     def add_pins(self):
         # inputs to wordline_driver.
         for i in range(self.rows):
-            self.add_pin("in_{0}".format(i))
+            self.add_pin("in_{0}".format(i), "INPUT")
         # Outputs from wordline_driver.
         for i in range(self.rows):
-            self.add_pin("wl_{0}".format(i))
-        self.add_pin("en")
-        self.add_pin("vdd")
-        self.add_pin("gnd")
+            self.add_pin("wl_{0}".format(i), "OUTPUT")
+        self.add_pin("en", "INPUT")
+        self.add_pin("vdd", "POWER")
+        self.add_pin("gnd", "GROUND")
 
 
     def add_modules(self):
diff --git a/compiler/modules/write_driver_array.py b/compiler/modules/write_driver_array.py
index 5f71b038..1b152e89 100644
--- a/compiler/modules/write_driver_array.py
+++ b/compiler/modules/write_driver_array.py
@@ -59,17 +59,17 @@ class write_driver_array(design.design):
 
     def add_pins(self):
         for i in range(self.word_size):
-            self.add_pin("data_{0}".format(i))
+            self.add_pin("data_{0}".format(i), "INPUT")
         for i in range(self.word_size):            
-            self.add_pin("bl_{0}".format(i))
-            self.add_pin("br_{0}".format(i))
+            self.add_pin("bl_{0}".format(i), "OUTPUT")
+            self.add_pin("br_{0}".format(i), "OUTPUT")
         if self.write_size != None:
             for i in range(self.num_wmasks):
-                self.add_pin("en_{}".format(i))
+                self.add_pin("en_{}".format(i), "INPUT")
         else:
-            self.add_pin("en")
-        self.add_pin("vdd")
-        self.add_pin("gnd")
+            self.add_pin("en", "INPUT")
+        self.add_pin("vdd", "POWER")
+        self.add_pin("gnd", "GROUND")
 
     def add_modules(self):
         self.driver = factory.create(module_type="write_driver")
diff --git a/compiler/pgates/pand2.py b/compiler/pgates/pand2.py
index 546eb830..d299cc56 100644
--- a/compiler/pgates/pand2.py
+++ b/compiler/pgates/pand2.py
@@ -47,11 +47,11 @@ class pand2(pgate.pgate):
         self.DRC_LVS()
         
     def add_pins(self):
-        self.add_pin("A")
-        self.add_pin("B")
-        self.add_pin("Z")
-        self.add_pin("vdd")
-        self.add_pin("gnd")
+        self.add_pin("A", "INPUT")
+        self.add_pin("B", "INPUT")
+        self.add_pin("Z", "OUTPUT")
+        self.add_pin("vdd", "POWER")
+        self.add_pin("gnd", "GROUND")
 
     def create_insts(self):
         self.nand_inst=self.add_inst(name="pand2_nand",
diff --git a/compiler/pgates/pbuf.py b/compiler/pgates/pbuf.py
index 6ccc8c16..125a1190 100644
--- a/compiler/pgates/pbuf.py
+++ b/compiler/pgates/pbuf.py
@@ -42,10 +42,10 @@ class pbuf(pgate.pgate):
         self.add_layout_pins()
         
     def add_pins(self):
-        self.add_pin("A")
-        self.add_pin("Z")
-        self.add_pin("vdd")
-        self.add_pin("gnd")
+        self.add_pin("A", "INPUT")
+        self.add_pin("Z", "OUTPUT")
+        self.add_pin("vdd", "POWER")
+        self.add_pin("gnd", "GROUND")
 
     def create_modules(self):
         # Shield the cap, but have at least a stage effort of 4
diff --git a/compiler/pgates/pdriver.py b/compiler/pgates/pdriver.py
index 8ea68e6e..a3180006 100644
--- a/compiler/pgates/pdriver.py
+++ b/compiler/pgates/pdriver.py
@@ -53,15 +53,15 @@ class pdriver(pgate.pgate):
             elif not self.neg_polarity and (self.num_stages%2): 
                 self.num_stages += 1
 
-        self.size_list = []
-        # compute sizes backwards from the fanout
-        fanout_prev = self.fanout
-        for x in range(self.num_stages):
-            fanout_prev = max(round(fanout_prev/self.stage_effort),1)
-            self.size_list.append(fanout_prev)
+            self.size_list = []
+            # compute sizes backwards from the fanout
+            fanout_prev = self.fanout
+            for x in range(self.num_stages):
+                fanout_prev = max(round(fanout_prev/self.stage_effort),1)
+                self.size_list.append(fanout_prev)
 
-        # reverse the sizes to be from input to output
-        self.size_list.reverse()
+            # reverse the sizes to be from input to output
+            self.size_list.reverse()
 
 
     def create_netlist(self):
@@ -81,10 +81,10 @@ class pdriver(pgate.pgate):
         
         
     def add_pins(self):
-        self.add_pin("A")
-        self.add_pin("Z")
-        self.add_pin("vdd")
-        self.add_pin("gnd")
+        self.add_pin("A", "INPUT")
+        self.add_pin("Z", "OUTPUT")
+        self.add_pin("vdd", "POWER")
+        self.add_pin("gnd", "GROUND")
 
     def add_modules(self):     
         self.inv_list = []
@@ -178,7 +178,7 @@ class pdriver(pgate.pgate):
         return self.inv_list[0].input_load()
 
     def analytical_delay(self, corner, slew, load=0.0):
-        """Calculate the analytical delay of INV1 -> ... -> INVn"""
+        """ Calculate the analytical delay of INV1 -> ... -> INVn """
 
         cout_list = []
         for prev_inv,inv in zip(self.inv_list, self.inv_list[1:]):
@@ -198,9 +198,12 @@ class pdriver(pgate.pgate):
             
         return delay
 
-
+    def get_sizes(self):
+        """ Return the relative sizes of the buffers """
+        return self.size_list
+    
     def get_stage_efforts(self, external_cout, inp_is_rise=False):
-        """Get the stage efforts of the A -> Z path"""
+        """ Get the stage efforts of the A -> Z path """
         cout_list = []
         for prev_inv,inv in zip(self.inv_list, self.inv_list[1:]):
             cout_list.append(inv.get_cin())
@@ -217,5 +220,5 @@ class pdriver(pgate.pgate):
         return stage_effort_list
 
     def get_cin(self):
-        """Returns the relative capacitance of the input"""
+        """ Returns the relative capacitance of the input """
         return self.inv_list[0].get_cin()
diff --git a/compiler/pgates/pinv.py b/compiler/pgates/pinv.py
index 906a009d..773a0452 100644
--- a/compiler/pgates/pinv.py
+++ b/compiler/pgates/pinv.py
@@ -60,7 +60,7 @@ class pinv(pgate.pgate):
     def add_pins(self):
         """ Adds pins for spice netlist """
         pin_list = ["A", "Z", "vdd", "gnd"]
-        dir_list = ['INPUT', 'OUTPUT', 'POWER', 'GROUND']
+        dir_list = ["INPUT", "OUTPUT", "POWER", "GROUND"]
         self.add_pin_list(pin_list, dir_list)
 
 
@@ -300,4 +300,4 @@ class pinv(pgate.pgate):
 
     def build_graph(self, graph, inst_name, port_nets):        
         """Adds edges based on inputs/outputs. Overrides base class function."""
-        self.add_graph_edges(graph, port_nets)    
\ No newline at end of file
+        self.add_graph_edges(graph, port_nets)    
diff --git a/compiler/pgates/pnand2.py b/compiler/pgates/pnand2.py
index 6e3fb7ae..956f0a30 100644
--- a/compiler/pgates/pnand2.py
+++ b/compiler/pgates/pnand2.py
@@ -61,7 +61,7 @@ class pnand2(pgate.pgate):
     def add_pins(self):
         """ Adds pins for spice netlist """
         pin_list = ["A", "B", "Z", "vdd", "gnd"]
-        dir_list = ['INPUT', 'INPUT', 'OUTPUT', 'POWER', 'GROUND']
+        dir_list = ["INPUT", "INPUT", "OUTPUT", "POWER", "GROUND"]
         self.add_pin_list(pin_list, dir_list)
 
         
@@ -281,4 +281,4 @@ class pnand2(pgate.pgate):
 
     def build_graph(self, graph, inst_name, port_nets):        
         """Adds edges based on inputs/outputs. Overrides base class function."""
-        self.add_graph_edges(graph, port_nets) 
\ No newline at end of file
+        self.add_graph_edges(graph, port_nets) 
diff --git a/compiler/pgates/pnand3.py b/compiler/pgates/pnand3.py
index a8cce176..30da9165 100644
--- a/compiler/pgates/pnand3.py
+++ b/compiler/pgates/pnand3.py
@@ -44,7 +44,7 @@ class pnand3(pgate.pgate):
     def add_pins(self):
         """ Adds pins for spice netlist """
         pin_list = ["A", "B", "C", "Z", "vdd", "gnd"]
-        dir_list = ['INPUT', 'INPUT', 'INPUT', 'OUTPUT', 'POWER', 'GROUND']
+        dir_list = ["INPUT", "INPUT", "INPUT", "OUTPUT", "POWER", "GROUND"]
         self.add_pin_list(pin_list, dir_list)
 
     def create_netlist(self):
@@ -283,4 +283,4 @@ class pnand3(pgate.pgate):
 
     def build_graph(self, graph, inst_name, port_nets):        
         """Adds edges based on inputs/outputs. Overrides base class function."""
-        self.add_graph_edges(graph, port_nets) 
\ No newline at end of file
+        self.add_graph_edges(graph, port_nets) 
diff --git a/compiler/pgates/pnor2.py b/compiler/pgates/pnor2.py
index 7f026da3..fa52c528 100644
--- a/compiler/pgates/pnor2.py
+++ b/compiler/pgates/pnor2.py
@@ -41,7 +41,7 @@ class pnor2(pgate.pgate):
     def add_pins(self):
         """ Adds pins for spice netlist """
         pin_list = ["A", "B", "Z", "vdd", "gnd"]
-        dir_list = ['INPUT', 'INPUT', 'OUTPUT', 'INOUT', 'INOUT']
+        dir_list = ["INPUT", "INPUT", "OUTPUT", "INOUT", "INOUT"]
         self.add_pin_list(pin_list, dir_list)
 
     def create_netlist(self):
@@ -242,4 +242,4 @@ class pnor2(pgate.pgate):
         
     def build_graph(self, graph, inst_name, port_nets):        
         """Adds edges based on inputs/outputs. Overrides base class function."""
-        self.add_graph_edges(graph, port_nets) 
\ No newline at end of file
+        self.add_graph_edges(graph, port_nets) 
diff --git a/compiler/pgates/precharge.py b/compiler/pgates/precharge.py
index 4e37aeea..b4423bed 100644
--- a/compiler/pgates/precharge.py
+++ b/compiler/pgates/precharge.py
@@ -53,7 +53,7 @@ class precharge(design.design):
         self.connect_to_bitlines()
 
     def add_pins(self):
-        self.add_pin_list(["bl", "br", "en_bar", "vdd"])
+        self.add_pin_list(["bl", "br", "en_bar", "vdd"], ["OUTPUT", "OUTPUT", "INPUT", "POWER"])
 
     def add_ptx(self):
         """