mirror of https://github.com/VLSIDA/OpenRAM.git
Correct elsif to elif
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@ -171,7 +171,7 @@ def setup_bitcell():
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# If we have non-1rw ports,
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# If we have non-1rw ports,
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# and the user didn't over-ride the bitcell manually,
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# and the user didn't over-ride the bitcell manually,
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# figure out the right bitcell to use
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# figure out the right bitcell to use
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elsif (OPTs.bitcell=="bitcell" and OPTS.replica_bitcell=="replica_bitcell"):
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elif (OPTs.bitcell=="bitcell" and OPTS.replica_bitcell=="replica_bitcell"):
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ports = ""
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ports = ""
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if OPTS.num_rw_ports>0:
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if OPTS.num_rw_ports>0:
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ports += "{}rw_".format(OPTS.num_rw_ports)
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ports += "{}rw_".format(OPTS.num_rw_ports)
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