From ab7a83b7a50c910818a3e2eed6feae2a02884806 Mon Sep 17 00:00:00 2001 From: Matt Guthaus Date: Sat, 20 Oct 2018 15:20:15 -0700 Subject: [PATCH] Remove old setup.tcl and edit one in tech dir --- compiler/verify/magic.py | 20 -------------------- technology/scn4m_subm/mag_lib/setup.tcl | 1 + 2 files changed, 1 insertion(+), 20 deletions(-) diff --git a/compiler/verify/magic.py b/compiler/verify/magic.py index 0df7fe24..bb116da3 100644 --- a/compiler/verify/magic.py +++ b/compiler/verify/magic.py @@ -99,26 +99,6 @@ def write_netgen_script(cell_name, sp_name): f.close() os.system("chmod u+x {}".format(run_file)) - setup_file = OPTS.openram_temp + "setup.tcl" - f = open(setup_file, "w") - f.write("ignore class c\n") - f.write("equate class {{nfet {0}.spice}} {{n {1}}}\n".format(cell_name, sp_name)) - f.write("equate class {{pfet {0}.spice}} {{p {1}}}\n".format(cell_name, sp_name)) - # This circuit has symmetries and needs to be flattened to resolve them or the banks won't pass - # Is there a more elegant way to add this when needed? - f.write("flatten class {{{0}.spice bitcell_array}}\n".format(cell_name)) - f.write("flatten class {{{0}.spice precharge_array_1}}\n".format(cell_name)) - f.write("flatten class {{{0}.spice precharge_array_2}}\n".format(cell_name)) - f.write("flatten class {{{0}.spice precharge_array_3}}\n".format(cell_name)) - f.write("flatten class {{{0}.spice precharge_array_4}}\n".format(cell_name)) - f.write("property {{nfet {0}.spice}} remove as ad ps pd\n".format(cell_name)) - f.write("property {{pfet {0}.spice}} remove as ad ps pd\n".format(cell_name)) - f.write("property {{n {0}}} remove as ad ps pd\n".format(sp_name)) - f.write("property {{p {0}}} remove as ad ps pd\n".format(sp_name)) - f.write("permute transistors\n") - f.write("permute pins n source drain\n") - f.write("permute pins p source drain\n") - f.close() def run_drc(cell_name, gds_name, extract=False, final_verification=False): """Run DRC check on a cell which is implemented in gds_name.""" diff --git a/technology/scn4m_subm/mag_lib/setup.tcl b/technology/scn4m_subm/mag_lib/setup.tcl index af55a416..caf7550b 100644 --- a/technology/scn4m_subm/mag_lib/setup.tcl +++ b/technology/scn4m_subm/mag_lib/setup.tcl @@ -4,6 +4,7 @@ equate class {-circuit1 nfet} {-circuit2 n} equate class {-circuit1 pfet} {-circuit2 p} # This circuit has symmetries and needs to be flattened to resolve them # or the banks won't pass +flatten class {-circuit1 bitcell_array} flatten class {-circuit1 precharge_array_1} flatten class {-circuit1 precharge_array_2} flatten class {-circuit1 precharge_array_3}