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Update golden delays. Fix uninitialized boolean.

This commit is contained in:
Matt Guthaus 2019-08-05 15:45:59 -07:00
parent 4d11de64ac
commit aae8566ff2
3 changed files with 42 additions and 42 deletions
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4
compiler/characterizer/delay.py
View File

@ -835,6 +835,7 @@ class delay(simulation):
Checks the measurements which represent the internal storage voltages
at the end of the read cycle.
"""
success = False
for polarity, meas_list in self.bit_meas.items():
for meas in meas_list:
val = meas.retrieve_measure()
@ -855,12 +856,11 @@ class delay(simulation):
elif (meas_cycle == sram_op.WRITE_ONE and polarity == bit_polarity.INVERTING) or\
(meas_cycle == sram_op.WRITE_ZERO and polarity == bit_polarity.NONINVERTING):
success = val < self.vdd_voltage/2
else:
success = False
if not success:
debug.info(1,("Wrong value detected on probe bit during read/write cycle. "
"Check writes and control logic for bugs.\n measure={}, op={}, "
"bit_storage={}, V(bit)={}").format(meas.name, meas_cycle.name, polarity.name,val))
return success
def check_bitline_meas(self, v_discharged_bl, v_charged_bl):

40
compiler/tests/21_hspice_delay_test.py
View File

@ -61,27 +61,27 @@ class timing_sram_test(openram_test):
data.update(port_data[0])
if OPTS.tech_name == "freepdk45":
golden_data = {'delay_hl': [0.2179763],
'delay_lh': [0.2179763],
'leakage_power': 0.0025727,
'min_period': 0.527,
'read0_power': [0.4479132],
'read1_power': [0.422467],
'slew_hl': [0.0988916],
'slew_lh': [0.0988916],
'write0_power': [0.4976688],
'write1_power': [0.4605285]}
golden_data = {'delay_hl': [0.2181231],
'delay_lh': [0.2181231],
'leakage_power': 0.0025453999999999997,
'min_period': 0.781,
'read0_power': [0.34664159999999994],
'read1_power': [0.32656349999999995],
'slew_hl': [0.21136519999999998],
'slew_lh': [0.21136519999999998],
'write0_power': [0.37980179999999997],
'write1_power': [0.3532026]}
elif OPTS.tech_name == "scn4m_subm":
golden_data = {'delay_hl': [1.4119000000000002],
'delay_lh': [1.4119000000000002],
'leakage_power': 0.027366399999999996,
'min_period': 3.125,
'read0_power': [14.7569],
'read1_power': [14.008800000000003],
'slew_hl': [0.7314153],
'slew_lh': [0.7314153],
'write0_power': [16.700500000000005],
'write1_power': [15.214100000000002]}
golden_data = {'delay_hl': [1.4082],
'delay_lh': [1.4082],
'leakage_power': 0.0267388,
'min_period': 4.688,
'read0_power': [11.5255],
'read1_power': [10.9406],
'slew_hl': [1.2979],
'slew_lh': [1.2979],
'write0_power': [12.9458],
'write1_power': [11.7444]}
else:
self.assertTrue(False) # other techs fail
# Check if no too many or too few results

40
compiler/tests/21_ngspice_delay_test.py
View File

@ -54,27 +54,27 @@ class timing_sram_test(openram_test):
data.update(port_data[0])
if OPTS.tech_name == "freepdk45":
golden_data = {'delay_hl': [0.2265453],
'delay_lh': [0.2265453],
'leakage_power': 0.003688569,
'min_period': 0.547,
'read0_power': [0.4418831],
'read1_power': [0.41914969999999996],
'slew_hl': [0.103665],
'slew_lh': [0.103665],
'write0_power': [0.48889660000000007],
'write1_power': [0.4419755]}
golden_data = {'delay_hl': [0.2179763],
'delay_lh': [0.2179763],
'leakage_power': 0.0025727,
'min_period': 0.527,
'read0_power': [0.4479132],
'read1_power': [0.422467],
'slew_hl': [0.0988916],
'slew_lh': [0.0988916],
'write0_power': [0.4976688],
'write1_power': [0.4605285]}
elif OPTS.tech_name == "scn4m_subm":
golden_data = {'delay_hl': [1.710243],
'delay_lh': [1.710243],
'leakage_power': 0.06079017,
'min_period': 3.75,
'read0_power': [14.046140000000001],
'read1_power': [13.52625],
'slew_hl': [0.7730236],
'slew_lh': [0.7730236],
'write0_power': [15.86152],
'write1_power': [14.612160000000001]}
golden_data = {'delay_hl': [1.708615],
'delay_lh': [1.708615],
'leakage_power': 0.06831667,
'min_period': 5.312,
'read0_power': [11.68257],
'read1_power': [11.20223],
'slew_hl': [1.391469],
'slew_lh': [1.391469],
'write0_power': [13.101120000000002],
'write1_power': [11.99391]}
else:
self.assertTrue(False) # other techs fail