mirror of https://github.com/VLSIDA/OpenRAM.git
Add fudge factor to pbitcell wells
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@ -983,10 +983,12 @@ class pbitcell(bitcell_base.bitcell_base):
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self.read_nmos.well_height)
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self.read_nmos.well_height)
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well_height = max_nmos_well_height + self.port_ypos \
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well_height = max_nmos_well_height + self.port_ypos \
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- self.nwell_enclose_active - self.gnd_position.y
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- self.nwell_enclose_active - self.gnd_position.y
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offset = vector(self.leftmost_xpos, self.botmost_ypos)
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# FIXME fudge factor xpos
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well_width = self.width + 2*self.nwell_enclose_active
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offset = vector(self.leftmost_xpos - self.nwell_enclose_active, self.botmost_ypos)
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self.add_rect(layer="pwell",
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self.add_rect(layer="pwell",
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offset=offset,
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offset=offset,
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width=self.width,
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width=well_width,
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height=well_height)
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height=well_height)
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# extend nwell to encompass inverter_pmos
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# extend nwell to encompass inverter_pmos
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@ -1003,7 +1005,8 @@ class pbitcell(bitcell_base.bitcell_base):
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well_height = self.vdd_position.y - inverter_well_ypos \
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well_height = self.vdd_position.y - inverter_well_ypos \
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+ self.nwell_enclose_active + drc["minwidth_tx"]
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+ self.nwell_enclose_active + drc["minwidth_tx"]
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offset = [inverter_well_xpos, inverter_well_ypos]
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# FIXME fudge factor xpos
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offset = [inverter_well_xpos + 2*self.nwell_enclose_active, inverter_well_ypos]
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self.add_rect(layer="nwell",
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self.add_rect(layer="nwell",
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offset=offset,
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offset=offset,
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width=well_width,
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width=well_width,
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