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Initial two port bank in SCMOS

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This commit is contained in:
Matt Guthaus
2018-11-13 16:05:22 -08:00
parent 732f35a362
commit aa779a7f82
13 changed files with 620 additions and 391 deletions
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compiler/modules/multibank.py
+4 -4
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@@ -54,8 +54,8 @@ class multibank(design.design):
self.compute_sizes()
self.add_pins()
self.create_modules()
self.add_modules()
self.create_instances()
self.setup_layout_constraints()
# FIXME: Move this to the add modules function
@@ -111,7 +111,7 @@ class multibank(design.design):
self.route_supplies()
def add_modules(self):
def create_instances(self):
""" Add modules. The order should not matter! """
# Above the bitcell array
@@ -175,8 +175,8 @@ class multibank(design.design):
def create_modules(self):
""" Create all the modules using the class loader """
def add_modules(self):
""" Add all the modules using the class loader """
self.tri = self.mod_tri_gate()
self.bitcell = self.mod_bitcell()