Initial two port bank in SCMOS

compiler/modules/bank_select.py

@@ -27,12 +27,12 @@ class bank_select(design.design):
     def create_netlist(self):
         self.add_pins()
         self.add_modules()
-        self.create_modules()
+        self.create_instances()
         
     def create_layout(self):
         self.calculate_module_offsets()
-        self.place_modules()
-        self.route_modules()
+        self.place_instances()
+        self.route_instances()
 
         self.DRC_LVS()
 
@@ -99,7 +99,7 @@ class bank_select(design.design):
         self.height = self.yoffset_maxpoint + 2*self.m1_pitch
         self.width = self.xoffset_inv + self.inv4x.width
         
-    def create_modules(self):
+    def create_instances(self):
         
         self.bank_sel_inv=self.add_inst(name="bank_sel_inv", 
                                         mod=self.inv_sel)
@@ -152,7 +152,7 @@ class bank_select(design.design):
                                    "vdd",
                                    "gnd"])
 
-    def place_modules(self):
+    def place_instances(self):
         
         # bank select inverter
         self.bank_select_inv_position = vector(self.xoffset_bank_sel_inv, 0)
@@ -195,7 +195,7 @@ class bank_select(design.design):
                            mirror=mirror)
             
 
-    def route_modules(self):
+    def route_instances(self):
         
         # bank_sel is vertical wire
         bank_sel_inv_pin = self.bank_sel_inv.get_pin("A")

compiler/modules/bitcell_array.py

@@ -34,7 +34,7 @@ class bitcell_array(design.design):
         """ Create and connect the netlist """
         self.add_modules()
         self.add_pins()
-        self.create_modules()
+        self.create_instances()
 
     def create_layout(self):
 
@@ -85,7 +85,7 @@ class bitcell_array(design.design):
         self.cell = self.mod_bitcell()
         self.add_mod(self.cell)
 
-    def create_modules(self):
+    def create_instances(self):
         """ Create the module instances used in this design """
         self.cell_inst = {}
         for col in range(self.column_size):

compiler/modules/control_logic.py

@@ -41,12 +41,12 @@ class control_logic(design.design):
         self.setup_signal_busses()
         self.add_pins()
         self.add_modules()
-        self.create_modules()
+        self.create_instances()
         
     def create_layout(self):
         """ Create layout and route between modules """
         self.route_rails()
-        self.place_modules()
+        self.place_instances()
         self.route_all()
         
         #self.add_lvs_correspondence_points()
@@ -155,8 +155,8 @@ class control_logic(design.design):
         self.rail_offsets = self.create_vertical_bus("metal2", self.m2_pitch, offset, self.internal_bus_list, height)
             
             
-    def create_modules(self):
-        """ Create all the modules """
+    def create_instances(self):
+        """ Create all the instances """
         self.create_dffs()
         self.create_clk_row()
         if (self.port_type == "rw") or (self.port_type == "w"):
@@ -167,8 +167,8 @@ class control_logic(design.design):
             self.create_rbl()
 
 
-    def place_modules(self):
-        """ Place all the modules """
+    def place_instances(self):
+        """ Place all the instances """
         # Keep track of all right-most instances to determine row boundary
         # and add the vdd/gnd pins
         self.row_end_inst = []

compiler/modules/dff_buf.py

@@ -36,13 +36,13 @@ class dff_buf(design.design):
     def create_netlist(self):
         self.add_modules()
         self.add_pins()
-        self.create_modules()
+        self.create_instances()
 
     def create_layout(self):
         self.width = self.dff.width + self.inv1.width + self.inv2.width
         self.height = self.dff.height
         
-        self.place_modules()
+        self.place_instances()
         self.route_wires()
         self.add_layout_pins()
         self.DRC_LVS()
@@ -70,7 +70,7 @@ class dff_buf(design.design):
         self.add_pin("vdd")
         self.add_pin("gnd")
 
-    def create_modules(self):
+    def create_instances(self):
         self.dff_inst=self.add_inst(name="dff_buf_dff",
                                     mod=self.dff)
         self.connect_inst(["D", "qint", "clk", "vdd", "gnd"])
@@ -83,7 +83,7 @@ class dff_buf(design.design):
                                      mod=self.inv2)
         self.connect_inst(["Qb", "Q",  "vdd", "gnd"])
 
-    def place_modules(self):
+    def place_instances(self):
         # Add the DFF
         self.dff_inst.place(vector(0,0))
 

compiler/modules/hierarchical_predecode.py

@@ -31,8 +31,8 @@ class hierarchical_predecode(design.design):
         self.add_pin("vdd")
         self.add_pin("gnd")
 
-    def create_modules(self):
-        """ Create the INV and NAND gate """
+    def add_modules(self):
+        """ Add the INV and NAND gate modules """
         
         self.inv = pinv()
         self.add_mod(self.inv)

compiler/modules/hierarchical_predecode2x4.py

@@ -18,7 +18,7 @@ class hierarchical_predecode2x4(hierarchical_predecode):
 
     def create_netlist(self):
         self.add_pins()
-        self.create_modules()
+        self.add_modules()
         self.create_input_inverters()
         self.create_output_inverters()
         connections =[["inbar_0", "inbar_1", "Z_0", "vdd", "gnd"],

compiler/modules/hierarchical_predecode3x8.py

@@ -18,7 +18,7 @@ class hierarchical_predecode3x8(hierarchical_predecode):
 
     def create_netlist(self):
         self.add_pins()
-        self.create_modules()
+        self.add_modules()
         self.create_input_inverters()
         self.create_output_inverters()
         connections=[["inbar_0", "inbar_1", "inbar_2", "Z_0", "vdd", "gnd"],

compiler/modules/multibank.py

@@ -54,8 +54,8 @@ class multibank(design.design):
         
         self.compute_sizes()
         self.add_pins()
-        self.create_modules()
         self.add_modules()
+        self.create_instances()
         self.setup_layout_constraints()
 
         # FIXME: Move this to the add modules function
@@ -111,7 +111,7 @@ class multibank(design.design):
         
         self.route_supplies()
         
-    def add_modules(self):
+    def create_instances(self):
         """ Add modules. The order should not matter! """
 
         # Above the bitcell array
@@ -175,8 +175,8 @@ class multibank(design.design):
 
 
 
-    def create_modules(self):
-        """ Create all the modules using the class loader """
+    def add_modules(self):
+        """ Add all the modules using the class loader """
         self.tri = self.mod_tri_gate()
         self.bitcell = self.mod_bitcell()
         

compiler/modules/replica_bitline.py

@@ -29,11 +29,11 @@ class replica_bitline(design.design):
     def create_netlist(self):
         self.add_modules()
         self.add_pins()
-        self.create_modules()
+        self.create_instances()
 
     def create_layout(self):
         self.calculate_module_offsets()
-        self.place_modules()
+        self.place_instances()
         self.route()
         self.add_layout_pins()
 
@@ -104,7 +104,7 @@ class replica_bitline(design.design):
         self.access_tx = ptx(tx_type="pmos")
         self.add_mod(self.access_tx)
 
-    def create_modules(self):
+    def create_instances(self):
         """ Create all of the module instances in the logical netlist """
         
         # This is the threshold detect inverter on the output of the RBL
@@ -152,7 +152,7 @@ class replica_bitline(design.design):
         self.wl_list = self.rbl.cell.list_all_wl_names()
         self.bl_list = self.rbl.cell.list_all_bl_names()
         
-    def place_modules(self):
+    def place_instances(self):
         """ Add all of the module instances in the logical netlist """
         
         # This is the threshold detect inverter on the output of the RBL

compiler/modules/wordline_driver.py

@@ -129,16 +129,15 @@ class wordline_driver(design.design):
         nand2_xoffset = inv1_xoffset + self.inv.width
         inv2_xoffset = nand2_xoffset + self.nand2.width
         
-        self.width = inv2_xoffset + self.inv.height
-        driver_height = self.inv.height
+        self.width = inv2_xoffset + self.inv.width
         self.height = self.inv.height * self.rows
         
         for row in range(self.rows):
             if (row % 2):
-                y_offset = driver_height*(row + 1)
+                y_offset = self.inv.height*(row + 1)
                 inst_mirror = "MX"
             else:
-                y_offset = driver_height*row
+                y_offset = self.inv.height*row
                 inst_mirror = "R0"
 
             inv1_offset = [inv1_xoffset, y_offset]