mirror of https://github.com/VLSIDA/OpenRAM.git
Cleaned the char_data to fit the previous style. Added print statements to load/slew sims.
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@ -46,6 +46,7 @@ class delay():
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self.period = 0
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self.set_load_slew(0,0)
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self.set_corner(corner)
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self.create_port_names()
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def set_corner(self,corner):
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""" Set the corner values """
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@ -640,12 +641,11 @@ class delay():
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"""
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Main function to characterize an SRAM for a table. Computes both delay and power characterization.
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"""
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#Dict to hold all characterization values
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char_data = {}
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self.set_probe(probe_address, probe_data)
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self.create_port_names()
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self.create_char_data_dict()
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self.load=max(loads)
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self.slew=max(slews)
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# This is for debugging a full simulation
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@ -659,7 +659,7 @@ class delay():
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# sys.exit(1)
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#For debugging, skips characterization and returns dummy values.
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# char_data = self.char_data
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# char_data = self.get_empty_measure_data_dict()
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# i = 1.0
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# for slew in slews:
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# for load in loads:
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@ -684,20 +684,22 @@ class delay():
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min_period = self.find_min_period(feasible_delays_lh, feasible_delays_hl)
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debug.check(type(min_period)==float,"Couldn't find minimum period.")
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debug.info(1, "Min Period Found: {0}ns".format(min_period))
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self.char_data["min_period"] = round_time(min_period)
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char_data["min_period"] = round_time(min_period)
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# 3) Find the leakage power of the trimmmed and UNtrimmed arrays.
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(full_array_leakage, trim_array_leakage)=self.run_power_simulation()
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self.char_data["leakage_power"]=full_array_leakage
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char_data["leakage_power"]=full_array_leakage
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leakage_offset = full_array_leakage - trim_array_leakage
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# 4) At the minimum period, measure the delay, slew and power for all slew/load pairs.
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self.simulate_loads_and_slews(slews, loads, leakage_offset)
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load_slew_data = self.simulate_loads_and_slews(slews, loads, leakage_offset)
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char_data.update(load_slew_data)
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return self.char_data
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return char_data
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def simulate_loads_and_slews(self, slews, loads, leakage_offset):
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"""Simulate all specified output loads and input slews pairs"""
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"""Simulate all specified output loads and input slews pairs of all ports"""
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measure_data = self.get_empty_measure_data_dict()
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#Set the target simulation ports to all available ports. This make sims slower but failed sims exit anyways.
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self.targ_read_ports = self.read_ports
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self.targ_write_ports = self.write_ports
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@ -707,12 +709,14 @@ class delay():
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# Find the delay, dynamic power, and leakage power of the trimmed array.
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(success, delay_results) = self.run_delay_simulation()
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debug.check(success,"Couldn't run a simulation. slew={0} load={1}\n".format(self.slew,self.load))
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debug.info(1, "Successful simulation on all ports. slew={0} load={1}".format(self.slew,self.load))
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for k,v in delay_results.items():
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if "power" in k:
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# Subtract partial array leakage and add full array leakage for the power measures
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self.char_data[k].append(v + leakage_offset)
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measure_data[k].append(v + leakage_offset)
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else:
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self.char_data[k].append(v)
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measure_data[k].append(v)
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return measure_data
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def add_data(self, data, port):
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""" Add the array of data values """
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@ -1038,11 +1042,12 @@ class delay():
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self.targ_read_ports = self.read_ports
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self.targ_write_ports = self.write_ports
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def create_char_data_dict(self):
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"""Make a dict of lists for each type of measurement to append results to"""
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def get_empty_measure_data_dict(self):
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"""Make a dict of lists for each type of delay and power measurement to append results to"""
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#Making this a member variable may not be the best option, but helps reduce code clutter
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self.char_data = {}
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measure_data = {}
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for port in range(self.total_port_num):
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for m in ["delay_lh", "delay_hl", "slew_lh", "slew_hl", "read0_power",
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"read1_power", "write0_power", "write1_power"]:
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self.char_data ["{0}{1}".format(m,port)]=[]
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measure_data ["{0}{1}".format(m,port)]=[]
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return measure_data
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