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Fix syntax error.

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mrg
2020-11-21 07:16:45 -08:00
parent 4c75bc003e
commit aa03eec943
1 changed files with 1 additions and 1 deletions
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compiler/modules/replica_bitcell_array.py
+1 -1
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@@ -338,8 +338,8 @@ class replica_bitcell_array(bitcell_base_array):
self.translate_all(array_offset.scale(-1, -1))
# Add extra width on the left and right for the unused WLs
self.height = self.dummy_row_insts[1].uy()
self.width = self.dummy_col_insts[1].rx() + self.unused_offset.x
self.height = self.dummy_row_insts[1].uy()
self.add_layout_pins()