From aa03eec9432cd995342738ca175d4e1c140d4ec8 Mon Sep 17 00:00:00 2001 From: mrg Date: Sat, 21 Nov 2020 07:16:45 -0800 Subject: [PATCH] Fix syntax error. --- compiler/modules/replica_bitcell_array.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/compiler/modules/replica_bitcell_array.py b/compiler/modules/replica_bitcell_array.py index ac9432c2..a2494f1b 100644 --- a/compiler/modules/replica_bitcell_array.py +++ b/compiler/modules/replica_bitcell_array.py @@ -338,8 +338,8 @@ class replica_bitcell_array(bitcell_base_array): self.translate_all(array_offset.scale(-1, -1)) # Add extra width on the left and right for the unused WLs - self.height = self.dummy_row_insts[1].uy() self.width = self.dummy_col_insts[1].rx() + self.unused_offset.x + self.height = self.dummy_row_insts[1].uy() self.add_layout_pins()