From a87b40e1cb5dcee21f9e3ff7a8e6dcfcd58dc739 Mon Sep 17 00:00:00 2001
From: Bugra Onal <onalbugra@gmail.com>
Date: Thu, 16 Jun 2022 15:12:43 -0700
Subject: [PATCH] Added conditional sections to template

---
 compiler/tests/sram_1b_16_1rw_scn4m_subm.log |  2 --
 compiler/tests/sram_1b_16_1rw_sky130.log     |  3 ---
 compiler/verilog_template/template.py        |  1 -
 compiler/verilog_template/test.py            | 20 --------------------
 4 files changed, 26 deletions(-)
 delete mode 100644 compiler/tests/sram_1b_16_1rw_scn4m_subm.log
 delete mode 100644 compiler/tests/sram_1b_16_1rw_sky130.log
 delete mode 100644 compiler/verilog_template/test.py

diff --git a/compiler/tests/sram_1b_16_1rw_scn4m_subm.log b/compiler/tests/sram_1b_16_1rw_scn4m_subm.log
deleted file mode 100644
index 1d80b5f9..00000000
--- a/compiler/tests/sram_1b_16_1rw_scn4m_subm.log
+++ /dev/null
@@ -1,2 +0,0 @@
-ERROR: file magic.py: line 358: sram	LVS mismatch (results in /tmp/openram_bugra_12868_temp/sram.lvs.report)
-
diff --git a/compiler/tests/sram_1b_16_1rw_sky130.log b/compiler/tests/sram_1b_16_1rw_sky130.log
deleted file mode 100644
index f6367750..00000000
--- a/compiler/tests/sram_1b_16_1rw_sky130.log
+++ /dev/null
@@ -1,3 +0,0 @@
-ERROR: file design.py: line 47: Custom cell pin names do not match spice file:
-['D', 'Q', 'CLK', 'VDD', 'GND'] vs []
-
diff --git a/compiler/verilog_template/template.py b/compiler/verilog_template/template.py
index b898af56..a6c9dab0 100644
--- a/compiler/verilog_template/template.py
+++ b/compiler/verilog_template/template.py
@@ -25,7 +25,6 @@ class loopSection(baseSection):
     """
 
     def __init__(self, var, key):
-        self.children = []
         self.var = var
         self.key = key
 
diff --git a/compiler/verilog_template/test.py b/compiler/verilog_template/test.py
deleted file mode 100644
index 228b5042..00000000
--- a/compiler/verilog_template/test.py
+++ /dev/null
@@ -1,20 +0,0 @@
-from template import template
-
-dict = {
-        'module_name': 'sram_1kbyte_32b_2bank', 
-        'bank_module_name': 'sram_1kbyte_32b_2bank_1bank', 
-        'vdd': 'vdd', 
-        'gnd': 'gnd', 
-        'ports': [0, 1], 
-        'rw_ports': [0], 
-        'r_ports': [1], 
-        'w_ports': [],
-        'banks': [0, 1],
-        'data_width': 32, 
-        'addr_width': 8,
-        'bank_sel': 1,
-        'num_wmask': 4
-        }
-t = template('../sram/sram_multibank_template.v', dict)
-t.write(dict['module_name'] + '.v')
-