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Template section clone method

This commit is contained in:
Bugra Onal 2022-03-09 08:58:29 -08:00
parent 5bbb8eae4c
commit a7db6d182e
2 changed files with 4 additions and 0 deletions
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2
compiler/base/verilog.py
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@ -38,6 +38,8 @@ class verilog:
self.template.setTextDict('GND', self.gnd_name) self.template.setTextDict('GND', self.gnd_name)
for port in self.all_ports: for port in self.all_ports:
self.template.cloneSection("PORTS", "PORTS" + str(port))
if port in self.readwrite_ports: if port in self.readwrite_ports:
self.vf.write("// Port {0}: RW\n".format(port)) self.vf.write("// Port {0}: RW\n".format(port))
elif port in self.read_ports: elif port in self.read_ports:

2
compiler/base/verilog_template.v
View File

@ -6,6 +6,7 @@
#>WRITE_SIZE_CMT #>WRITE_SIZE_CMT
module #$MODULE_NAME$# ( module #$MODULE_NAME$# (
#<PORTS
`ifdef USE_POWER_PINS `ifdef USE_POWER_PINS
#$VDD$#, #$VDD$#,
#$GND$#, #$GND$#,
@ -28,6 +29,7 @@ module #$MODULE_NAME$# (
// Port #$PORT_NUM$#: W // Port #$PORT_NUM$#: W
clk#$PORT_NUM#$,csb#$PORT_NUM$#,web$#PORT_NUM$#,addr#PORT_NUM$#,din#PORT_NUM$# clk#$PORT_NUM#$,csb#$PORT_NUM$#,web$#PORT_NUM$#,addr#PORT_NUM$#,din#PORT_NUM$#
#>W_PORT #>W_PORT
#>PORTS
); );
#<WMASK_PAR #<WMASK_PAR
parameter NUM_WMASK = #$NUM_WMASK#$ ; parameter NUM_WMASK = #$NUM_WMASK#$ ;