diff --git a/compiler/base/verilog.py b/compiler/base/verilog.py
index d0edfdbf..a2978925 100644
--- a/compiler/base/verilog.py
+++ b/compiler/base/verilog.py
@@ -38,6 +38,8 @@ class verilog:
         self.template.setTextDict('GND', self.gnd_name)
 
         for port in self.all_ports:
+            self.template.cloneSection("PORTS", "PORTS" + str(port))
+            
             if port in self.readwrite_ports:
                 self.vf.write("// Port {0}: RW\n".format(port))
             elif port in self.read_ports:
diff --git a/compiler/base/verilog_template.v b/compiler/base/verilog_template.v
index c033410e..2c40b767 100644
--- a/compiler/base/verilog_template.v
+++ b/compiler/base/verilog_template.v
@@ -6,6 +6,7 @@
 #>WRITE_SIZE_CMT
 
 module #$MODULE_NAME$# (
+#<PORTS
 `ifdef USE_POWER_PINS
     #$VDD$#,
     #$GND$#,
@@ -28,6 +29,7 @@ module #$MODULE_NAME$# (
 // Port #$PORT_NUM$#: W
     clk#$PORT_NUM#$,csb#$PORT_NUM$#,web$#PORT_NUM$#,addr#PORT_NUM$#,din#PORT_NUM$#
 #>W_PORT
+#>PORTS
   );
 #<WMASK_PAR
   parameter NUM_WMASK = #$NUM_WMASK#$ ;