Changed verilog file naming convention

2026-08-29 01:24:39 +02:00 · 2022-08-18 10:36:54 -07:00
parent 1a23d156c0
commit a7c6406d0d
1 changed files with 2 additions and 2 deletions
@@ -58,10 +58,10 @@ class sram():

    def verilog_write(self, name):
        if self.num_banks != 1:
-            self.s.verilog_write(name[:-2] + '_1bank.v')
+            self.s.verilog_write(name)
            from .sram_multibank import sram_multibank
            mb = sram_multibank(self.s)
-            mb.verilog_write(name)
+            mb.verilog_write(name[:-2] + '_top.v')
        else:
            self.s.verilog_write(name)