From a7c6406d0d6480a9d3e797e2f98993f4ba0800cb Mon Sep 17 00:00:00 2001 From: Bugra Onal Date: Thu, 18 Aug 2022 10:36:54 -0700 Subject: [PATCH] Changed verilog file naming convention --- compiler/modules/sram.py | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/compiler/modules/sram.py b/compiler/modules/sram.py index 019c4edb..52a54688 100644 --- a/compiler/modules/sram.py +++ b/compiler/modules/sram.py @@ -58,10 +58,10 @@ class sram(): def verilog_write(self, name): if self.num_banks != 1: - self.s.verilog_write(name[:-2] + '_1bank.v') + self.s.verilog_write(name) from .sram_multibank import sram_multibank mb = sram_multibank(self.s) - mb.verilog_write(name) + mb.verilog_write(name[:-2] + '_top.v') else: self.s.verilog_write(name)