mirror of
https://github.com/VLSIDA/OpenRAM.git
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Move precharge and column mux cells to pgate directory.
Move gnd to M3 in column mux. Create column mux cell unit test.
This commit is contained in:
Matt Guthaus
@@ -1,213 +0,0 @@
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import contact
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import pgate
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import debug
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from tech import drc, parameter
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from ptx import ptx
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from vector import vector
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from globals import OPTS
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class precharge(pgate.pgate):
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"""
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Creates a single precharge cell
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This module implements the precharge bitline cell used in the design.
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"""
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def __init__(self, name, size=1):
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pgate.pgate.__init__(self, name)
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debug.info(2, "create single precharge cell: {0}".format(name))
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c = reload(__import__(OPTS.bitcell))
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self.mod_bitcell = getattr(c, OPTS.bitcell)
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self.bitcell = self.mod_bitcell()
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self.beta = parameter["beta"]
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self.ptx_width = self.beta*parameter["min_tx_size"]
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self.width = self.bitcell.width
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self.add_pins()
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self.create_layout()
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self.DRC_LVS()
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def add_pins(self):
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self.add_pin_list(["bl", "br", "en", "vdd"])
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def create_layout(self):
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self.create_ptx()
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self.add_ptx()
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self.connect_poly()
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self.add_en()
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self.add_nwell_and_contact()
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self.add_vdd_rail()
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self.add_bitlines()
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self.connect_to_bitlines()
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def create_ptx(self):
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"""Initializes the upper and lower pmos"""
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self.pmos = ptx(width=self.ptx_width,
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tx_type="pmos")
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self.add_mod(self.pmos)
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# Compute the other pmos2 location, but determining offset to overlap the
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# source and drain pins
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self.overlap_offset = self.pmos.get_pin("D").ll() - self.pmos.get_pin("S").ll()
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def add_vdd_rail(self):
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"""Adds a vdd rail at the top of the cell"""
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# adds the rail across the width of the cell
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vdd_position = vector(0, self.height - self.m1_width)
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self.add_rect(layer="metal1",
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offset=vdd_position,
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width=self.width,
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height=self.m1_width)
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pmos_pin = self.upper_pmos2_inst.get_pin("S")
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# center of vdd rail
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vdd_pos = vector(pmos_pin.cx(), vdd_position.y + 0.5*self.m1_width)
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self.add_path("metal1", [pmos_pin.uc(), vdd_pos])
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# Add the M1->M2->M3 stack at the left edge
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self.add_via_center(layers=("metal1", "via1", "metal2"),
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offset=vdd_pos.scale(0,1))
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self.add_via_center(layers=("metal2", "via2", "metal3"),
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offset=vdd_pos.scale(0,1))
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self.add_layout_pin_rect_center(text="vdd",
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layer="metal3",
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offset=vdd_pos.scale(0,1))
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def add_ptx(self):
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"""Adds both the upper_pmos and lower_pmos to the module"""
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# adds the lower pmos to layout
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#base = vector(self.width - 2*self.pmos.width + self.overlap_offset.x, 0)
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self.lower_pmos_position = vector(self.bitcell.get_pin("BL").lx(),
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self.pmos.active_offset.y)
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self.lower_pmos_inst=self.add_inst(name="lower_pmos",
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mod=self.pmos,
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offset=self.lower_pmos_position)
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self.connect_inst(["bl", "en", "BR", "vdd"])
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# adds the upper pmos(s) to layout
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ydiff = self.pmos.height + 2*self.m1_space + contact.poly.width
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self.upper_pmos1_pos = self.lower_pmos_position + vector(0, ydiff)
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self.upper_pmos1_inst=self.add_inst(name="upper_pmos1",
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mod=self.pmos,
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offset=self.upper_pmos1_pos)
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self.connect_inst(["bl", "en", "vdd", "vdd"])
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upper_pmos2_pos = self.upper_pmos1_pos + self.overlap_offset
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self.upper_pmos2_inst=self.add_inst(name="upper_pmos2",
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mod=self.pmos,
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offset=upper_pmos2_pos)
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self.connect_inst(["br", "en", "vdd", "vdd"])
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def connect_poly(self):
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"""Connects the upper and lower pmos together"""
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offset = self.lower_pmos_inst.get_pin("G").ll()
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# connects the top and bottom pmos' gates together
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ylength = self.upper_pmos1_inst.get_pin("G").ll().y - offset.y
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self.add_rect(layer="poly",
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offset=offset,
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width=self.poly_width,
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height=ylength)
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# connects the two poly for the two upper pmos(s)
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offset = offset + vector(0, ylength - self.poly_width)
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xlength = self.upper_pmos2_inst.get_pin("G").lx() - self.upper_pmos1_inst.get_pin("G").lx() + self.poly_width
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self.add_rect(layer="poly",
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offset=offset,
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width=xlength,
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height=self.poly_width)
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def add_en(self):
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"""Adds the en input rail, en contact/vias, and connects to the pmos"""
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# adds the en contact to connect the gates to the en rail on metal1
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offset = self.lower_pmos_inst.get_pin("G").ul() + vector(0,0.5*self.poly_space)
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self.add_contact_center(layers=("poly", "contact", "metal1"),
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offset=offset,
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rotate=90)
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# adds the en rail on metal1
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self.add_layout_pin_segment_center(text="en",
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layer="metal1",
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start=offset.scale(0,1),
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end=offset.scale(0,1)+vector(self.width,0))
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def add_nwell_and_contact(self):
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"""Adds a nwell tap to connect to the vdd rail"""
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# adds the contact from active to metal1
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well_contact_pos = self.upper_pmos1_inst.get_pin("D").center().scale(1,0) \
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+ vector(0, self.upper_pmos1_inst.uy() + contact.well.height/2 + drc["well_extend_active"])
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self.add_contact_center(layers=("active", "contact", "metal1"),
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offset=well_contact_pos,
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implant_type="n",
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well_type="n")
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self.height = well_contact_pos.y + contact.well.height
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self.add_rect(layer="nwell",
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offset=vector(0,0),
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width=self.width,
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height=self.height)
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def add_bitlines(self):
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"""Adds both bit-line and bit-line-bar to the module"""
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# adds the BL on metal 2
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offset = vector(self.bitcell.get_pin("BL").cx(),0) - vector(0.5 * self.m2_width,0)
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self.add_layout_pin(text="bl",
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layer="metal2",
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offset=offset,
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width=drc['minwidth_metal2'],
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height=self.height)
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# adds the BR on metal 2
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offset = vector(self.bitcell.get_pin("BR").cx(),0) - vector(0.5 * self.m2_width,0)
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self.add_layout_pin(text="br",
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layer="metal2",
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offset=offset,
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width=drc['minwidth_metal2'],
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height=self.height)
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def connect_to_bitlines(self):
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self.add_bitline_contacts()
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self.connect_pmos(self.lower_pmos_inst.get_pin("S"),self.get_pin("bl"))
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self.connect_pmos(self.lower_pmos_inst.get_pin("D"),self.get_pin("br"))
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self.connect_pmos(self.upper_pmos1_inst.get_pin("S"),self.get_pin("bl"))
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self.connect_pmos(self.upper_pmos2_inst.get_pin("D"),self.get_pin("br"))
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def add_bitline_contacts(self):
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"""Adds contacts/via from metal1 to metal2 for bit-lines"""
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stack=("metal1", "via1", "metal2")
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pos = self.lower_pmos_inst.get_pin("S").center()
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self.add_contact_center(layers=stack,
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offset=pos)
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pos = self.lower_pmos_inst.get_pin("D").center()
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self.add_contact_center(layers=stack,
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offset=pos)
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pos = self.upper_pmos1_inst.get_pin("S").center()
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self.add_contact_center(layers=stack,
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offset=pos)
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pos = self.upper_pmos2_inst.get_pin("D").center()
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self.add_contact_center(layers=stack,
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offset=pos)
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def connect_pmos(self, pmos_pin, bit_pin):
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""" Connect pmos pin to bitline pin """
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ll_pos = vector(min(pmos_pin.lx(),bit_pin.lx()), pmos_pin.by())
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ur_pos = vector(max(pmos_pin.rx(),bit_pin.rx()), pmos_pin.uy())
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width = ur_pos.x-ll_pos.x
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height = ur_pos.y-ll_pos.y
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self.add_rect(layer="metal2",
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offset=ll_pos,
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width=width,
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height=height)
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@@ -62,13 +62,29 @@ class sense_amp_array(design.design):
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br_offset = amp_position + br_pin.ll().scale(1,0)
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dout_offset = amp_position + dout_pin.ll()
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self.add_inst(name=name,
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inst = self.add_inst(name=name,
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mod=self.amp,
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offset=amp_position)
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self.connect_inst(["bl[{0}]".format(i),"br[{0}]".format(i),
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"data[{0}]".format(i/self.words_per_row),
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"en", "vdd", "gnd"])
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gnd_pos = inst.get_pin("gnd").center()
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self.add_via_center(layers=("metal2", "via2", "metal3"),
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offset=gnd_pos)
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self.add_layout_pin_rect_center(text="gnd",
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layer="metal3",
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offset=gnd_pos)
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vdd_pos = inst.get_pin("vdd").center()
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self.add_via_center(layers=("metal2", "via2", "metal3"),
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offset=vdd_pos)
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self.add_layout_pin_rect_center(text="vdd",
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layer="metal3",
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offset=vdd_pos)
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self.add_layout_pin(text="bl[{0}]".format(i),
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layer="metal2",
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offset=bl_offset,
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@@ -87,26 +103,7 @@ class sense_amp_array(design.design):
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height=dout_pin.height())
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def connect_rails(self):
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# add vdd rail across entire array
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vdd_offset = self.amp.get_pin("vdd").ll().scale(0,1)
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self.add_layout_pin(text="vdd",
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layer="metal1",
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offset=vdd_offset,
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width=self.width,
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height=drc["minwidth_metal1"])
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# NOTE:the gnd rails are vertical so it is not connected horizontally
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# add gnd rail across entire array
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gnd_offset = self.amp.get_pin("gnd").ll().scale(0,1)
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self.add_layout_pin(text="gnd",
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layer="metal1",
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offset=gnd_offset,
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width=self.width,
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height=drc["minwidth_metal1"])
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# add sclk rail across entire array
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sclk_offset = self.amp.get_pin("en").ll().scale(0,1)
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self.add_layout_pin(text="en",
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@@ -1,173 +0,0 @@
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import design
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import debug
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from tech import drc, info
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from vector import vector
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import contact
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from ptx import ptx
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from globals import OPTS
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class single_level_column_mux(design.design):
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"""
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This module implements the columnmux bitline cell used in the design.
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Creates a single columnmux cell.
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"""
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def __init__(self, tx_size):
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name="single_level_column_mux_{}".format(tx_size)
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design.design.__init__(self, name)
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debug.info(2, "create single column mux cell: {0}".format(name))
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c = reload(__import__(OPTS.bitcell))
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self.mod_bitcell = getattr(c, OPTS.bitcell)
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self.bitcell = self.mod_bitcell()
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self.ptx_width = tx_size * drc["minwidth_tx"]
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self.add_pin_list(["bl", "br", "bl_out", "br_out", "sel", "gnd"])
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self.create_layout()
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def create_layout(self):
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self.add_ptx()
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self.pin_height = 2*self.m2_width
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self.width = self.bitcell.width
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self.height = self.nmos2.uy() + self.pin_height
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self.connect_poly()
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self.add_gnd_rail()
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self.add_bitline_pins()
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self.connect_bitlines()
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self.add_wells()
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def add_bitline_pins(self):
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""" Add the top and bottom pins to this cell """
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bl_pos = vector(self.bitcell.get_pin("BL").lx(), 0)
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br_pos = vector(self.bitcell.get_pin("BR").lx(), 0)
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# bl and br
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self.add_layout_pin(text="bl",
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layer="metal2",
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offset=bl_pos + vector(0,self.height - self.pin_height),
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height=self.pin_height)
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self.add_layout_pin(text="br",
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layer="metal2",
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offset=br_pos + vector(0,self.height - self.pin_height),
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height=self.pin_height)
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# bl_out and br_out
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self.add_layout_pin(text="bl_out",
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layer="metal2",
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offset=bl_pos,
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height=self.pin_height)
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self.add_layout_pin(text="br_out",
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layer="metal2",
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offset=br_pos,
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height=self.pin_height)
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def add_ptx(self):
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""" Create the two pass gate NMOS transistors to switch the bitlines"""
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# Adds nmos1,nmos2 to the module
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self.nmos = ptx(width=self.ptx_width)
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self.add_mod(self.nmos)
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# Space it in the center
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nmos1_position = self.nmos.active_offset.scale(0,1) + vector(0.5*self.bitcell.width-0.5*self.nmos.active_width,0)
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self.nmos1=self.add_inst(name="mux_tx1",
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mod=self.nmos,
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offset=nmos1_position)
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self.connect_inst(["bl", "sel", "bl_out", "gnd"])
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# This aligns it directly above the other tx with gates abutting
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nmos2_position = nmos1_position + vector(0,self.nmos.active_height + self.poly_space)
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self.nmos2=self.add_inst(name="mux_tx2",
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mod=self.nmos,
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offset=nmos2_position)
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self.connect_inst(["br", "sel", "br_out", "gnd"])
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def connect_poly(self):
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""" Connect the poly gate of the two pass transistors """
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height=self.nmos2.get_pin("G").uy() - self.nmos1.get_pin("G").by()
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self.add_layout_pin(text="sel",
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layer="poly",
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offset=self.nmos1.get_pin("G").ll(),
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height=height)
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def connect_bitlines(self):
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""" Connect the bitlines to the mux transistors """
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# These are on metal2
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bl_pin = self.get_pin("bl")
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br_pin = self.get_pin("br")
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bl_out_pin = self.get_pin("bl_out")
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br_out_pin = self.get_pin("br_out")
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# These are on metal1
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nmos1_s_pin = self.nmos1.get_pin("S")
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nmos1_d_pin = self.nmos1.get_pin("D")
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nmos2_s_pin = self.nmos2.get_pin("S")
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nmos2_d_pin = self.nmos2.get_pin("D")
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# Add vias to bl, br_out, nmos2/S, nmos1/D
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self.add_via_center(layers=("metal1","via1","metal2"),
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offset=bl_pin.bc())
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self.add_via_center(layers=("metal1","via1","metal2"),
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offset=br_out_pin.uc())
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self.add_via_center(layers=("metal1","via1","metal2"),
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offset=nmos2_s_pin.center())
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self.add_via_center(layers=("metal1","via1","metal2"),
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offset=nmos1_d_pin.center())
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# bl -> nmos2/D on metal1
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# bl_out -> nmos2/S on metal2
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self.add_path("metal1",[bl_pin.ll(), vector(nmos2_d_pin.cx(),bl_pin.by()), nmos2_d_pin.center()])
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# halfway up, move over
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mid1 = bl_out_pin.uc().scale(1,0.5)+nmos2_s_pin.bc().scale(0,0.5)
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mid2 = bl_out_pin.uc().scale(0,0.5)+nmos2_s_pin.bc().scale(1,0.5)
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self.add_path("metal2",[bl_out_pin.uc(), mid1, mid2, nmos2_s_pin.bc()])
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# br -> nmos1/D on metal2
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# br_out -> nmos1/S on metal1
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self.add_path("metal1",[br_out_pin.uc(), vector(nmos1_s_pin.cx(),br_out_pin.uy()), nmos1_s_pin.center()])
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# halfway up, move over
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mid1 = br_pin.bc().scale(1,0.5)+nmos1_d_pin.uc().scale(0,0.5)
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mid2 = br_pin.bc().scale(0,0.5)+nmos1_d_pin.uc().scale(1,0.5)
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self.add_path("metal2",[br_pin.bc(), mid1, mid2, nmos1_d_pin.uc()])
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def add_gnd_rail(self):
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""" Add the gnd rails through the cell to connect to the bitcell array """
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gnd_pins = self.bitcell.get_pins("gnd")
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for gnd_pin in gnd_pins:
|
||||
# only use vertical gnd pins that span the whole cell
|
||||
if gnd_pin.layer == "metal2" and gnd_pin.height >= self.bitcell.height:
|
||||
gnd_position = vector(gnd_pin.lx(), 0)
|
||||
self.add_layout_pin(text="gnd",
|
||||
layer="metal2",
|
||||
offset=gnd_position,
|
||||
height=self.height)
|
||||
|
||||
def add_wells(self):
|
||||
""" Add a well and implant over the whole cell. Also, add the pwell contact (if it exists) """
|
||||
|
||||
# find right most gnd rail
|
||||
gnd_pins = self.bitcell.get_pins("gnd")
|
||||
right_gnd = None
|
||||
for gnd_pin in gnd_pins:
|
||||
if right_gnd == None or gnd_pin.lx()>right_gnd.lx():
|
||||
right_gnd = gnd_pin
|
||||
|
||||
# Add to the right (first) gnd rail
|
||||
m1m2_offset = right_gnd.bc() + vector(0,0.5*self.nmos.poly_height)
|
||||
self.add_via_center(layers=("metal1", "via1", "metal2"),
|
||||
offset=m1m2_offset)
|
||||
active_offset = right_gnd.bc() + vector(0,0.5*self.nmos.poly_height)
|
||||
self.add_via_center(layers=("active", "contact", "metal1"),
|
||||
offset=active_offset,
|
||||
implant_type="p",
|
||||
well_type="p")
|
||||
|
||||
|
||||
@@ -100,16 +100,9 @@ class single_level_column_mux_array(design.design):
|
||||
offset=offset,
|
||||
height=self.height-offset.y)
|
||||
|
||||
gnd_pins = mux_inst.get_pins("gnd")
|
||||
for gnd_pin in gnd_pins:
|
||||
# only do even colums to avoid duplicates
|
||||
offset = gnd_pin.ll()
|
||||
if col_num % 2 == 0:
|
||||
self.add_layout_pin(text="gnd",
|
||||
layer="metal2",
|
||||
offset=offset.scale(1,0),
|
||||
height=self.height)
|
||||
|
||||
for inst in self.mux_inst:
|
||||
self.copy_layout_pin(inst, "gnd")
|
||||
|
||||
|
||||
def add_routing(self):
|
||||
self.add_horizontal_input_rail()
|
||||
|
||||
Reference in New Issue
Block a user