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Begin implementing a write mask layout as the port data level.

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jsowash
2019-08-07 09:12:21 -07:00
parent a4a72a9639
commit a6bb410560
5 changed files with 203 additions and 44 deletions
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compiler/modules/write_driver_array.py
+14 -6
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@@ -95,6 +95,7 @@ class write_driver_array(design.design):
"br_{0}".format(index),
"en_{0}".format(windex), "vdd", "gnd"])
w+=1
# when w equals write size, the next en pin can be connected since we are now at the next wmask bit
if w == self.write_size:
w = 0
windex+=1
@@ -149,12 +150,19 @@ class write_driver_array(design.design):
self.add_layout_pin_rect_center(text=n,
layer="metal3",
offset=pin_pos)
self.add_layout_pin(text="en",
layer="metal1",
offset=self.driver_insts[0].get_pin("en").ll().scale(0,1),
width=self.width,
height=drc('minwidth_metal1'))
if self.write_size is not None:
for bit in range(self.num_wmasks):
self.add_layout_pin(text="en_{}".format(bit),
layer="metal1",
offset=self.driver_insts[bit*(self.write_size-1)].get_pin("en").ll().scale(0,1),
width=self.width,
height=drc('minwidth_metal1'))
else:
self.add_layout_pin(text="en",
layer="metal1",
offset=self.driver_insts[0].get_pin("en").ll().scale(0,1),
width=self.width,
height=drc('minwidth_metal1'))