luke
/
OpenRAM
mirror of https://github.com/VLSIDA/OpenRAM.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

Merge branch 'dev' into add_wmask

This commit is contained in:
jsowash 2019-08-01 13:49:52 -07:00
parent e4d8ba90a5 7ba97ee0ba
commit a4a72a9639
5 changed files with 17 additions and 18 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

6
compiler/characterizer/functional.py
View File

@ -6,6 +6,7 @@
# All rights reserved.
#
import sys,re,shutil
import collections
from design import design
import debug
import math
@ -52,7 +53,8 @@ class functional(simulation):
# Number of checks can be changed
self.num_cycles = 15
self.stored_words = {}
# This is to have ordered keys for random selection
self.stored_words = collections.OrderedDict()
self.write_check = []
self.read_check = []
@ -258,7 +260,7 @@ class functional(simulation):
def get_data(self):
""" Gets an available address and corresponding word. """
# Currently unused but may need later depending on how the functional test develops
addr = random.choice(sort(list(self.stored_words.keys())))
addr = random.choice(list(self.stored_words.keys()))
word = self.stored_words[addr]
return (addr,word)

14
compiler/modules/bank.py
View File

@ -100,7 +100,7 @@ class bank(design.design):
self.add_pin("bank_sel{}".format(port),"INPUT")
for port in self.read_ports:
self.add_pin("s_en{0}".format(port), "INPUT")
for port in self.read_ports:
for port in self.all_ports:
self.add_pin("p_en_bar{0}".format(port), "INPUT")
for port in self.write_ports:
self.add_pin("w_en{0}".format(port), "INPUT")
@ -309,7 +309,7 @@ class bank(design.design):
self.input_control_signals.append(["wl_en{}".format(port_num), "w_en{}".format(port_num), "s_en{}".format(port_num), "p_en_bar{}".format(port_num), "rbl_wl{}".format(port_num)])
port_num += 1
for port in range(OPTS.num_w_ports):
self.input_control_signals.append(["wl_en{}".format(port_num), "w_en{}".format(port_num)])
self.input_control_signals.append(["wl_en{}".format(port_num), "w_en{}".format(port_num), "p_en_bar{}".format(port_num)])
port_num += 1
for port in range(OPTS.num_r_ports):
self.input_control_signals.append(["wl_en{}".format(port_num), "s_en{}".format(port_num), "p_en_bar{}".format(port_num), "rbl_wl{}".format(port_num)])
@ -463,8 +463,7 @@ class bank(design.design):
temp.extend(sel_names)
if port in self.read_ports:
temp.append("s_en{0}".format(port))
if port in self.read_ports:
temp.append("p_en_bar{0}".format(port))
temp.append("p_en_bar{0}".format(port))
if port in self.write_ports:
temp.append("w_en{0}".format(port))
for bit in range(self.num_wmasks):
@ -618,8 +617,8 @@ class bank(design.design):
bank_sel_signals = ["clk_buf", "w_en", "s_en", "p_en_bar", "bank_sel"]
gated_bank_sel_signals = ["gated_clk_buf", "gated_w_en", "gated_s_en", "gated_p_en_bar"]
elif self.port_id[port] == "w":
bank_sel_signals = ["clk_buf", "w_en", "bank_sel"]
gated_bank_sel_signals = ["gated_clk_buf", "gated_w_en"]
bank_sel_signals = ["clk_buf", "w_en", "p_en_bar", "bank_sel"]
gated_bank_sel_signals = ["gated_clk_buf", "gated_w_en", "gated_p_en_bar"]
else:
bank_sel_signals = ["clk_buf", "s_en", "p_en_bar", "bank_sel"]
gated_bank_sel_signals = ["gated_clk_buf", "gated_s_en", "gated_p_en_bar"]
@ -944,8 +943,7 @@ class bank(design.design):
read_inst = 0
connection = []
if port in self.read_ports:
connection.append((self.prefix+"p_en_bar{}".format(port), self.port_data_inst[port].get_pin("p_en_bar").lc()))
connection.append((self.prefix+"p_en_bar{}".format(port), self.port_data_inst[port].get_pin("p_en_bar").lc()))
if port in self.read_ports:
rbl_wl_name = self.bitcell_array.get_rbl_wl_name(self.port_rbl_map[port])

5
compiler/modules/control_logic.py
View File

@ -345,11 +345,12 @@ class control_logic(design.design):
# Outputs to the bank
if self.port_type == "rw":
self.output_list = ["rbl_wl", "s_en", "w_en", "p_en_bar"]
self.output_list = ["rbl_wl", "s_en", "w_en"]
elif self.port_type == "r":
self.output_list = ["rbl_wl", "s_en", "p_en_bar"]
self.output_list = ["rbl_wl", "s_en"]
else:
self.output_list = ["w_en"]
self.output_list.append("p_en_bar")
self.output_list.append("wl_en")
self.output_list.append("clk_buf")

3
compiler/modules/port_data.py
View File

@ -100,8 +100,7 @@ class port_data(design.design):
self.add_pin(pin_name,"INPUT")
if self.port in self.read_ports:
self.add_pin("s_en", "INPUT")
if self.port in self.read_ports:
self.add_pin("p_en_bar", "INPUT")
self.add_pin("p_en_bar", "INPUT")
if self.port in self.write_ports:
self.add_pin("w_en", "INPUT")
for bit in range(self.num_wmasks):

7
compiler/sram/sram_base.py
View File

@ -197,7 +197,7 @@ class sram_base(design, verilog, lef):
if self.port_id[port] == "r":
self.control_bus_names[port].extend([sen, pen])
elif self.port_id[port] == "w":
self.control_bus_names[port].extend([wen])
self.control_bus_names[port].extend([wen, pen])
else:
self.control_bus_names[port].extend([sen, wen, pen])
self.vert_control_bus_positions = self.create_vertical_bus(layer="metal2",
@ -354,7 +354,7 @@ class sram_base(design, verilog, lef):
temp.append("bank_sel{0}[{1}]".format(port,bank_num))
for port in self.read_ports:
temp.append("s_en{0}".format(port))
for port in self.read_ports:
for port in self.all_ports:
temp.append("p_en_bar{0}".format(port))
for port in self.write_ports:
temp.append("w_en{0}".format(port))
@ -513,8 +513,7 @@ class sram_base(design, verilog, lef):
temp.append("s_en{}".format(port))
if port in self.write_ports:
temp.append("w_en{}".format(port))
if port in self.read_ports:
temp.append("p_en_bar{}".format(port))
temp.append("p_en_bar{}".format(port))
temp.extend(["wl_en{}".format(port), "clk_buf{}".format(port), "vdd", "gnd"])
self.connect_inst(temp)