From a64ca423c6a364813c31cd15b64abe3f00373798 Mon Sep 17 00:00:00 2001 From: Michael Timothy Grimes Date: Thu, 12 Jul 2018 23:45:47 -0700 Subject: [PATCH] changing pbitcell_array test to include an important permutation of the design --- compiler/tests/05_pbitcell_array_test.py | 9 ++++++++- 1 file changed, 8 insertions(+), 1 deletion(-) mode change 100755 => 100644 compiler/tests/05_pbitcell_array_test.py diff --git a/compiler/tests/05_pbitcell_array_test.py b/compiler/tests/05_pbitcell_array_test.py old mode 100755 new mode 100644 index 2dfed383..c4ad0b32 --- a/compiler/tests/05_pbitcell_array_test.py +++ b/compiler/tests/05_pbitcell_array_test.py @@ -36,10 +36,17 @@ class array_multiport_test(openram_test): OPTS.r_ports = 0 OPTS.w_ports = 2 - debug.info(2, "Testing 4x4 array for multiport bitcell, with read/write ports at the edge of the bit cell") + debug.info(2, "Testing 4x4 array for multiport bitcell, with write ports at the edge of the bit cell") a = bitcell_array.bitcell_array(name="pbitcell_array", cols=4, rows=4) self.local_check(a) + OPTS.rw_ports = 2 + OPTS.r_ports = 0 + OPTS.w_ports = 0 + + debug.info(2, "Testing 4x4 array for multiport bitcell, with read/write ports at the edge of the bit cell") + a = bitcell_array.bitcell_array(name="pbitcell_array", cols=4, rows=4) + self.local_check(a) OPTS.bitcell = "bitcell" OPTS.check_lvsdrc = True