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Base-verilog

This commit is contained in:
Bugra Onal 2022-02-23 10:34:48 -08:00
parent 769633a459
commit a5728cdecc
1 changed files with 3 additions and 1 deletions
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4
compiler/base/verilog.py
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@ -7,6 +7,7 @@
# #
import math import math
from tech import spice from tech import spice
import verilog_template
class verilog: class verilog:
@ -15,7 +16,8 @@ class verilog:
This is inherited by the sram_base class. This is inherited by the sram_base class.
""" """
def __init__(self): def __init__(self):
pass self.template = verilog_template('verilog_template.v')
self.template.readTemplate()
def verilog_write(self, verilog_name): def verilog_write(self, verilog_name):
""" Write a behavioral Verilog model. """ """ Write a behavioral Verilog model. """