From a5728cdecc22019f924c25d6a49037c79a6b13dc Mon Sep 17 00:00:00 2001 From: Bugra Onal Date: Wed, 23 Feb 2022 10:34:48 -0800 Subject: [PATCH] Base-verilog --- compiler/base/verilog.py | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/compiler/base/verilog.py b/compiler/base/verilog.py index b40e174e..03d0e868 100644 --- a/compiler/base/verilog.py +++ b/compiler/base/verilog.py @@ -7,6 +7,7 @@ # import math from tech import spice +import verilog_template class verilog: @@ -15,7 +16,8 @@ class verilog: This is inherited by the sram_base class. """ def __init__(self): - pass + self.template = verilog_template('verilog_template.v') + self.template.readTemplate() def verilog_write(self, verilog_name): """ Write a behavioral Verilog model. """