mirror of https://github.com/VLSIDA/OpenRAM.git
Merge branch 'dev' into add_wmask
This commit is contained in:
commit
e4d8ba90a5
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@ -139,7 +139,6 @@ class functional(simulation):
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elif op == "write":
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addr = self.gen_addr()
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word = self.gen_data()
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# print("write",self.t_current,addr,word)
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# two ports cannot write to the same address
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if addr in w_addrs:
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self.add_noop_one_port("0"*self.addr_size, "0"*self.word_size, "0"*self.num_wmasks, port)
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@ -161,7 +160,6 @@ class functional(simulation):
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lower = bit * self.write_size
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upper = lower + self.write_size - 1
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new_word = new_word[:lower] + old_word[lower:upper+1] + new_word[upper + 1:]
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# print("partial_w",self.t_current,addr,wmask,word, "partial_w_word:", new_word)
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# two ports cannot write to the same address
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if addr in w_addrs:
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self.add_noop_one_port("0"*self.addr_size, "0"*self.word_size, "0"*self.num_wmasks, port)
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@ -172,7 +170,6 @@ class functional(simulation):
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w_addrs.append(addr)
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else:
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(addr,word) = random.choice(list(self.stored_words.items()))
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# print("read",self.t_current,addr,word)
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# cannot read from an address that is currently being written to
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if addr in w_addrs:
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self.add_noop_one_port("0"*self.addr_size, "0"*self.word_size, "0"*self.num_wmasks, port)
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@ -248,29 +245,20 @@ class functional(simulation):
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def gen_data(self):
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""" Generates a random word to write. """
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rand = random.randint(0,(2**self.word_size)-1)
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data_bits = self.convert_to_bin(rand,False)
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random_value = random.randint(0,(2**self.word_size)-1)
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data_bits = self.convert_to_bin(random_value,False)
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return data_bits
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def gen_data_all_bits(self):
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""" Generates a random word, either all 0's or all 1's, to write. """
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rand = random.randint(0,1)
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bits = []
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for bit in range(self.word_size):
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bits.append(rand)
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data_bits = ''.join(map(str,bits))
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return data_bits
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def gen_addr(self):
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""" Generates a random address value to write to. """
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rand = random.randint(0,(2**self.addr_size)-1)
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addr_bits = self.convert_to_bin(rand,True)
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random_value = random.randint(0,(2**self.addr_size)-1)
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addr_bits = self.convert_to_bin(random_value,True)
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return addr_bits
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def get_data(self):
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""" Gets an available address and corresponding word. """
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# Currently unused but may need later depending on how the functional test develops
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addr = random.choice(list(self.stored_words.keys()))
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addr = random.choice(sort(list(self.stored_words.keys())))
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word = self.stored_words[addr]
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return (addr,word)
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@ -280,6 +268,7 @@ class functional(simulation):
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if(is_addr):
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expected_value = self.addr_size
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else:
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expected_value = self.word_size
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for i in range (expected_value - len(new_value)):
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new_value = "0" + new_value
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Binary file not shown.
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@ -1,6 +1,6 @@
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magic
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tech scmos
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timestamp 1556015973
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timestamp 1564675126
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<< nwell >>
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rect -3 101 37 138
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rect -3 0 37 51
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@ -10,7 +10,6 @@ rect -3 51 37 101
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<< ntransistor >>
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rect 9 178 11 190
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rect 17 178 19 190
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rect 15 163 27 165
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rect 9 144 11 148
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rect 17 144 19 148
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rect 10 82 12 89
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@ -31,10 +30,6 @@ rect 8 178 9 190
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rect 11 178 12 190
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rect 16 178 17 190
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rect 19 178 20 190
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rect 15 165 27 166
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rect 15 162 27 163
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rect 12 158 15 161
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rect 12 156 16 158
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rect 8 144 9 148
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rect 11 144 12 148
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rect 16 144 17 148
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@ -71,8 +66,6 @@ rect 3 35 7 38
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rect 4 178 8 190
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rect 12 178 16 190
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rect 20 178 24 190
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rect 15 166 27 170
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rect 15 158 27 162
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rect 4 144 8 148
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rect 12 144 16 148
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rect 20 144 24 148
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@ -95,7 +88,6 @@ rect 11 38 15 45
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rect 19 38 23 45
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rect 27 38 31 45
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<< psubstratepcontact >>
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rect 12 152 16 156
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rect 26 82 30 89
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<< nsubstratencontact >>
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rect 12 118 16 122
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@ -109,8 +101,6 @@ rect 9 176 11 178
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rect 17 173 19 178
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rect 6 171 19 173
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rect 6 168 8 171
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rect 13 163 15 165
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rect 27 163 33 165
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rect 9 148 11 150
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rect 17 148 19 150
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rect 9 132 11 144
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@ -133,12 +123,9 @@ rect 18 89 20 90
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rect 10 81 12 82
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rect 10 79 13 81
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rect 2 71 3 75
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rect 11 71 13 79
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rect 11 67 13 79
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rect 18 79 20 82
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rect 18 77 23 79
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rect 31 71 33 163
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rect 11 69 33 71
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rect 11 67 13 69
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rect 8 65 13 67
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rect 8 64 10 65
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rect 16 64 18 66
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@ -164,13 +151,9 @@ rect 15 10 19 14
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rect 5 193 10 197
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rect 5 190 8 193
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rect 32 182 33 186
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rect 13 170 16 178
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rect 13 166 15 170
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rect 4 148 8 164
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rect 12 158 15 162
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rect 12 156 16 158
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rect 23 157 27 158
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rect 12 148 16 152
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rect 12 163 16 178
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rect 12 148 16 159
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rect 4 132 8 144
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rect 20 142 24 144
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rect 30 142 33 182
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@ -199,7 +182,7 @@ rect 11 24 36 28
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<< m2contact >>
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rect 10 193 14 197
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rect 20 190 24 194
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rect 23 153 27 157
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rect 12 159 16 163
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rect 16 118 20 122
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rect 26 89 30 90
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rect 26 86 30 89
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@ -220,7 +203,7 @@ rlabel m2contact 21 66 21 66 1 gnd
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rlabel m2contact 28 88 28 88 1 gnd
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rlabel m2contact 21 33 21 33 1 vdd
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rlabel m2contact 18 120 18 120 1 vdd
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rlabel m2contact 25 155 25 155 1 gnd
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rlabel metal2 12 201 12 201 5 bl
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rlabel metal2 22 201 22 201 5 br
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rlabel m2contact 14 161 14 161 1 gnd
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<< end >>
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@ -28,9 +28,8 @@ M_14 din_gated_bar din_gated gnd gnd n W=0.8u L=0.4u
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************************************************
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* pull down with en enable
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M_15 bl din_gated_bar net_5 gnd n W=2.4u L=0.4u
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M_16 br din_bar_gated_bar net_5 gnd n W=2.4u L=0.4u
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M_17 net_5 en gnd gnd n W=2.4u L=0.4u
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M_15 bl din_gated_bar gnd gnd n W=2.4u L=0.4u
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M_16 br din_bar_gated_bar gnd gnd n W=2.4u L=0.4u
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