mirror of
https://github.com/VLSIDA/OpenRAM.git
synced 2026-09-02 11:08:01 +02:00
First draft of sram_factory code
This commit is contained in:
Matt Guthaus
@@ -21,7 +21,7 @@ class pand2_test(openram_test):
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import pand2
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debug.info(2, "Testing pand2 gate 4x")
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a = pand2.pand2(4)
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a = pand2.pand2(name="pand2x4", size=4)
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self.local_check(a)
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globals.end_openram()
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@@ -10,84 +10,94 @@ sys.path.append(os.path.join(sys.path[0],".."))
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import globals
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from globals import OPTS
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import debug
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OPTS = globals.OPTS
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from sram_factory import factory
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#@unittest.skip("SKIPPING 04_pbitcell_test")
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class pbitcell_test(openram_test):
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def runTest(self):
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globals.init_openram("config_20_{0}".format(OPTS.tech_name))
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from pbitcell import pbitcell
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import tech
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OPTS.num_rw_ports=1
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OPTS.num_w_ports=1
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OPTS.num_r_ports=1
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factory.reset()
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debug.info(2, "Bitcell with 1 of each port: read/write, write, and read")
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tx = pbitcell()
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tx = pbitcell(name="pbc")
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self.local_check(tx)
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OPTS.num_rw_ports=0
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OPTS.num_w_ports=1
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OPTS.num_r_ports=1
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factory.reset()
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debug.info(2, "Bitcell with 0 read/write ports")
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tx = pbitcell()
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tx = pbitcell(name="pbc")
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self.local_check(tx)
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OPTS.num_rw_ports=1
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OPTS.num_w_ports=0
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OPTS.num_r_ports=1
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factory.reset()
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debug.info(2, "Bitcell with 0 write ports")
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tx = pbitcell()
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tx = pbitcell(name="pbc")
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self.local_check(tx)
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OPTS.num_rw_ports=1
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OPTS.num_w_ports=1
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OPTS.num_r_ports=0
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factory.reset()
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debug.info(2, "Bitcell with 0 read ports")
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tx = pbitcell()
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tx = pbitcell(name="pbc")
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self.local_check(tx)
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OPTS.num_rw_ports=1
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OPTS.num_w_ports=0
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OPTS.num_r_ports=0
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factory.reset()
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debug.info(2, "Bitcell with 0 read ports and 0 write ports")
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tx = pbitcell()
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tx = pbitcell(name="pbc")
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self.local_check(tx)
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OPTS.num_rw_ports=2
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OPTS.num_w_ports=2
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OPTS.num_r_ports=2
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factory.reset()
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debug.info(2, "Bitcell with 2 of each port: read/write, write, and read")
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tx = pbitcell()
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tx = pbitcell(name="pbc")
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self.local_check(tx)
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OPTS.num_rw_ports=0
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OPTS.num_w_ports=2
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OPTS.num_r_ports=2
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factory.reset()
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debug.info(2, "Bitcell with 0 read/write ports")
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tx = pbitcell()
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tx = pbitcell(name="pbc")
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self.local_check(tx)
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OPTS.num_rw_ports=2
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OPTS.num_w_ports=0
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OPTS.num_r_ports=2
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factory.reset()
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debug.info(2, "Bitcell with 0 write ports")
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tx = pbitcell()
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tx = pbitcell(name="pbc")
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self.local_check(tx)
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OPTS.num_rw_ports=2
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OPTS.num_w_ports=2
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OPTS.num_r_ports=0
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factory.reset()
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debug.info(2, "Bitcell with 0 read ports")
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tx = pbitcell()
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tx = pbitcell(name="pbc")
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self.local_check(tx)
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OPTS.num_rw_ports=2
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OPTS.num_w_ports=0
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OPTS.num_r_ports=0
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factory.reset()
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debug.info(2, "Bitcell with 0 read ports and 0 write ports")
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tx = pbitcell()
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tx = pbitcell(name="pbc")
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self.local_check(tx)
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globals.end_openram()
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@@ -21,7 +21,7 @@ class pbuf_test(openram_test):
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import pbuf
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debug.info(2, "Testing inverter/buffer 4x 8x")
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a = pbuf.pbuf(8)
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a = pbuf.pbuf(name="pbufx8", size=8)
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self.local_check(a)
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globals.end_openram()
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@@ -23,16 +23,21 @@ class pdriver_test(openram_test):
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debug.info(2, "Testing inverter/buffer 4x 8x")
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# a tests the error message for specifying conflicting conditions
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#a = pdriver.pdriver(fanout_size = 4,size_list = [1,2,4,8])
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b = pdriver.pdriver(size_list = [1,2,4,8])
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c = pdriver.pdriver(fanout_size = 50)
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d = pdriver.pdriver(fanout_size = 50, neg_polarity = True)
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e = pdriver.pdriver(fanout_size = 64)
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f = pdriver.pdriver(fanout_size = 64, neg_polarity = True)
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#self.local_check(a)
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b = pdriver.pdriver(name="pdriver1", size_list = [1,2,4,8])
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self.local_check(b)
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c = pdriver.pdriver(name="pdriver2", fanout_size = 50)
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self.local_check(c)
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d = pdriver.pdriver(name="pdriver3", fanout_size = 50, neg_polarity = True)
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self.local_check(d)
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e = pdriver.pdriver(name="pdriver4", fanout_size = 64)
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self.local_check(e)
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f = pdriver.pdriver(name="pdriver5", fanout_size = 64, neg_polarity = True)
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self.local_check(f)
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globals.end_openram()
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@@ -19,7 +19,7 @@ class pinv_test(openram_test):
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import tech
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debug.info(2, "Checking 10x inverter")
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tx = pinv.pinv(size=8)
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tx = pinv.pinv(name="pinvx10",size=8)
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self.local_check(tx)
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globals.end_openram()
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@@ -19,7 +19,7 @@ class pinv_test(openram_test):
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import tech
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debug.info(2, "Checking 1x beta=3 size inverter")
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tx = pinv.pinv(size=1, beta=3)
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tx = pinv.pinv(name="pinvx1b", size=1, beta=3)
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self.local_check(tx)
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globals.end_openram()
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@@ -18,7 +18,7 @@ class pinv_test(openram_test):
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import tech
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debug.info(2, "Checking 1x size inverter")
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tx = pinv.pinv(size=1)
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tx = pinv.pinv(name="pinvx1", size=1)
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self.local_check(tx)
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globals.end_openram()
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@@ -19,7 +19,7 @@ class pinv_test(openram_test):
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import tech
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debug.info(2, "Checking 2x size inverter")
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tx = pinv.pinv(size=2)
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tx = pinv.pinv(name="pinvx2", size=2)
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self.local_check(tx)
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globals.end_openram()
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@@ -18,7 +18,7 @@ class pinvbuf_test(openram_test):
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import pinvbuf
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debug.info(2, "Testing inverter/buffer 4x 8x")
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a = pinvbuf.pinvbuf(8)
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a = pinvbuf.pinvbuf(name="pinvufx8", size=8)
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self.local_check(a)
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globals.end_openram()
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@@ -21,7 +21,7 @@ class pnand2_test(openram_test):
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import tech
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debug.info(2, "Checking 2-input nand gate")
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tx = pnand2.pnand2(size=1)
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tx = pnand2.pnand2(name="pnand2", size=1)
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self.local_check(tx)
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globals.end_openram()
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@@ -21,7 +21,7 @@ class pnand3_test(openram_test):
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import tech
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debug.info(2, "Checking 3-input nand gate")
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tx = pnand3.pnand3(size=1)
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tx = pnand3.pnand3(name="pnand3", size=1)
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self.local_check(tx)
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globals.end_openram()
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@@ -21,7 +21,7 @@ class pnor2_test(openram_test):
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import tech
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debug.info(2, "Checking 2-input nor gate")
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tx = pnor2.pnor2(size=1)
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tx = pnor2.pnor2(name="pnor2", size=1)
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self.local_check(tx)
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globals.end_openram()
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@@ -10,6 +10,7 @@ sys.path.append(os.path.join(sys.path[0],".."))
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import globals
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from globals import OPTS
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import debug
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from sram_factory import factory
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class precharge_test(openram_test):
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@@ -28,7 +29,8 @@ class precharge_test(openram_test):
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OPTS.num_rw_ports = 1
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OPTS.num_r_ports = 1
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OPTS.num_w_ports = 1
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factory.reset()
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debug.info(2, "Checking precharge for pbitcell (innermost connections)")
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tx = precharge.precharge(name="precharge_driver", size=1, bitcell_bl="bl0", bitcell_br="br0")
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self.local_check(tx)
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@@ -10,29 +10,31 @@ sys.path.append(os.path.join(sys.path[0],".."))
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import globals
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from globals import OPTS
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import debug
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from sram_factory import factory
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class replica_pbitcell_test(openram_test):
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def runTest(self):
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globals.init_openram("config_20_{0}".format(OPTS.tech_name))
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import replica_pbitcell
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import tech
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OPTS.bitcell = "pbitcell"
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OPTS.num_rw_ports = 1
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OPTS.num_r_ports = 0
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OPTS.num_w_ports = 0
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factory.reset()
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debug.info(2, "Checking replica bitcell using pbitcell (small cell)")
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tx = replica_pbitcell.replica_pbitcell()
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tx = replica_pbitcell.replica_pbitcell(name="rpbc")
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self.local_check(tx)
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OPTS.num_rw_ports = 1
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OPTS.num_r_ports = 1
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OPTS.num_w_ports = 1
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factory.reset()
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debug.info(2, "Checking replica bitcell using pbitcell (large cell)")
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tx = replica_pbitcell.replica_pbitcell()
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tx = replica_pbitcell.replica_pbitcell(name="rpbc")
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self.local_check(tx)
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globals.end_openram()
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@@ -10,6 +10,7 @@ sys.path.append(os.path.join(sys.path[0],".."))
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import globals
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from globals import OPTS
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import debug
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from sram_factory import factory
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#@unittest.skip("SKIPPING 04_driver_test")
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@@ -22,7 +23,7 @@ class single_level_column_mux_test(openram_test):
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# check single level column mux in single port
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debug.info(2, "Checking column mux")
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tx = single_level_column_mux.single_level_column_mux(tx_size=8)
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tx = single_level_column_mux.single_level_column_mux(name="mux8", tx_size=8)
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self.local_check(tx)
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# check single level column mux in multi-port
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@@ -30,13 +31,15 @@ class single_level_column_mux_test(openram_test):
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OPTS.num_rw_ports = 1
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OPTS.num_r_ports = 1
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OPTS.num_w_ports = 1
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factory.reset()
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debug.info(2, "Checking column mux for pbitcell (innermost connections)")
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tx = single_level_column_mux.single_level_column_mux(tx_size=8, bitcell_bl="bl0", bitcell_br="br0")
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tx = single_level_column_mux.single_level_column_mux(name="mux8_2", tx_size=8, bitcell_bl="bl0", bitcell_br="br0")
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self.local_check(tx)
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factory.reset()
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debug.info(2, "Checking column mux for pbitcell (outermost connections)")
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tx = single_level_column_mux.single_level_column_mux(tx_size=8, bitcell_bl="bl2", bitcell_br="br2")
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tx = single_level_column_mux.single_level_column_mux(name="mux8_3", tx_size=8, bitcell_bl="bl2", bitcell_br="br2")
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self.local_check(tx)
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globals.end_openram()
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@@ -10,6 +10,7 @@ sys.path.append(os.path.join(sys.path[0],".."))
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import globals
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from globals import OPTS
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import debug
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from sram_factory import factory
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class hierarchical_decoder_test(openram_test):
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@@ -20,29 +21,29 @@ class hierarchical_decoder_test(openram_test):
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# Doesn't require hierarchical decoder
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# debug.info(1, "Testing 4 row sample for hierarchical_decoder")
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# a = hierarchical_decoder.hierarchical_decoder(rows=4)
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# a = hierarchical_decoder.hierarchical_decoder(name="hd1, rows=4)
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# self.local_check(a)
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# Doesn't require hierarchical decoder
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# debug.info(1, "Testing 8 row sample for hierarchical_decoder")
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# a = hierarchical_decoder.hierarchical_decoder(rows=8)
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# a = hierarchical_decoder.hierarchical_decoder(name="hd2", rows=8)
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# self.local_check(a)
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# check hierarchical decoder for single port
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debug.info(1, "Testing 16 row sample for hierarchical_decoder")
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a = hierarchical_decoder.hierarchical_decoder(rows=16)
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a = hierarchical_decoder.hierarchical_decoder(name="hd3", rows=16)
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self.local_check(a)
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debug.info(1, "Testing 32 row sample for hierarchical_decoder")
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a = hierarchical_decoder.hierarchical_decoder(rows=32)
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a = hierarchical_decoder.hierarchical_decoder(name="hd4", rows=32)
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self.local_check(a)
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debug.info(1, "Testing 128 row sample for hierarchical_decoder")
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a = hierarchical_decoder.hierarchical_decoder(rows=128)
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a = hierarchical_decoder.hierarchical_decoder(name="hd5", rows=128)
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self.local_check(a)
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debug.info(1, "Testing 512 row sample for hierarchical_decoder")
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a = hierarchical_decoder.hierarchical_decoder(rows=512)
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a = hierarchical_decoder.hierarchical_decoder(name="hd6", rows=512)
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self.local_check(a)
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# check hierarchical decoder for multi-port
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@@ -50,21 +51,22 @@ class hierarchical_decoder_test(openram_test):
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OPTS.num_rw_ports = 1
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OPTS.num_w_ports = 0
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OPTS.num_r_ports = 0
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factory.reset()
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debug.info(1, "Testing 16 row sample for hierarchical_decoder (multi-port case)")
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a = hierarchical_decoder.hierarchical_decoder(rows=16)
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a = hierarchical_decoder.hierarchical_decoder(name="hd7", rows=16)
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self.local_check(a)
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debug.info(1, "Testing 32 row sample for hierarchical_decoder (multi-port case)")
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a = hierarchical_decoder.hierarchical_decoder(rows=32)
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a = hierarchical_decoder.hierarchical_decoder(name="hd8", rows=32)
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self.local_check(a)
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debug.info(1, "Testing 128 row sample for hierarchical_decoder (multi-port case)")
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a = hierarchical_decoder.hierarchical_decoder(rows=128)
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a = hierarchical_decoder.hierarchical_decoder(name="hd9", rows=128)
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self.local_check(a)
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debug.info(1, "Testing 512 row sample for hierarchical_decoder (multi-port case)")
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a = hierarchical_decoder.hierarchical_decoder(rows=512)
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a = hierarchical_decoder.hierarchical_decoder(name="hd10", rows=512)
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self.local_check(a)
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globals.end_openram()
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@@ -20,7 +20,7 @@ class hierarchical_predecode2x4_test(openram_test):
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# checking hierarchical precode 2x4 for single port
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debug.info(1, "Testing sample for hierarchy_predecode2x4")
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a = pre.hierarchical_predecode2x4()
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a = pre.hierarchical_predecode2x4(name="pre1")
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self.local_check(a)
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# checking hierarchical precode 2x4 for multi-port
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@@ -30,7 +30,7 @@ class hierarchical_predecode2x4_test(openram_test):
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OPTS.num_r_ports = 0
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debug.info(1, "Testing sample for hierarchy_predecode2x4 (multi-port case)")
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a = pre.hierarchical_predecode2x4()
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a = pre.hierarchical_predecode2x4(name="pre2")
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self.local_check(a)
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globals.end_openram()
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@@ -20,7 +20,7 @@ class hierarchical_predecode3x8_test(openram_test):
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# checking hierarchical precode 3x8 for single port
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debug.info(1, "Testing sample for hierarchy_predecode3x8")
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a = pre.hierarchical_predecode3x8()
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a = pre.hierarchical_predecode3x8(name="pre1")
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self.local_check(a)
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# checking hierarchical precode 3x8 for multi-port
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@@ -30,7 +30,7 @@ class hierarchical_predecode3x8_test(openram_test):
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OPTS.num_r_ports = 0
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debug.info(1, "Testing sample for hierarchy_predecode3x8 (multi-port case)")
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a = pre.hierarchical_predecode3x8()
|
||||
a = pre.hierarchical_predecode3x8(name="pre2")
|
||||
self.local_check(a)
|
||||
|
||||
globals.end_openram()
|
||||
|
||||
@@ -9,6 +9,7 @@ sys.path.append(os.path.join(sys.path[0],".."))
|
||||
import globals
|
||||
from globals import OPTS
|
||||
import debug
|
||||
from sram_factory import factory
|
||||
|
||||
class single_level_column_mux_test(openram_test):
|
||||
|
||||
@@ -18,15 +19,15 @@ class single_level_column_mux_test(openram_test):
|
||||
|
||||
# check single level column mux array in single port
|
||||
debug.info(1, "Testing sample for 2-way column_mux_array")
|
||||
a = single_level_column_mux_array.single_level_column_mux_array(columns=16, word_size=8)
|
||||
a = single_level_column_mux_array.single_level_column_mux_array(name="mux1", columns=16, word_size=8)
|
||||
self.local_check(a)
|
||||
|
||||
debug.info(1, "Testing sample for 4-way column_mux_array")
|
||||
a = single_level_column_mux_array.single_level_column_mux_array(columns=16, word_size=4)
|
||||
a = single_level_column_mux_array.single_level_column_mux_array(name="mux2", columns=16, word_size=4)
|
||||
self.local_check(a)
|
||||
|
||||
debug.info(1, "Testing sample for 8-way column_mux_array")
|
||||
a = single_level_column_mux_array.single_level_column_mux_array(columns=32, word_size=4)
|
||||
a = single_level_column_mux_array.single_level_column_mux_array(name="mux3", columns=32, word_size=4)
|
||||
self.local_check(a)
|
||||
|
||||
# check single level column mux array in multi-port
|
||||
@@ -34,21 +35,22 @@ class single_level_column_mux_test(openram_test):
|
||||
OPTS.num_rw_ports = 1
|
||||
OPTS.num_r_ports = 1
|
||||
OPTS.num_w_ports = 1
|
||||
|
||||
|
||||
factory.reset()
|
||||
debug.info(1, "Testing sample for 2-way column_mux_array in multi-port")
|
||||
a = single_level_column_mux_array.single_level_column_mux_array(columns=16, word_size=8, bitcell_bl="bl0", bitcell_br="br0")
|
||||
a = single_level_column_mux_array.single_level_column_mux_array(name="mux4", columns=16, word_size=8, bitcell_bl="bl0", bitcell_br="br0")
|
||||
self.local_check(a)
|
||||
|
||||
debug.info(1, "Testing sample for 4-way column_mux_array in multi-port")
|
||||
a = single_level_column_mux_array.single_level_column_mux_array(columns=16, word_size=4, bitcell_bl="bl0", bitcell_br="br0")
|
||||
a = single_level_column_mux_array.single_level_column_mux_array(name="mux5", columns=16, word_size=4, bitcell_bl="bl0", bitcell_br="br0")
|
||||
self.local_check(a)
|
||||
|
||||
debug.info(1, "Testing sample for 8-way column_mux_array in multi-port (innermost connections)")
|
||||
a = single_level_column_mux_array.single_level_column_mux_array(columns=32, word_size=4, bitcell_bl="bl0", bitcell_br="br0")
|
||||
a = single_level_column_mux_array.single_level_column_mux_array(name="mux6", columns=32, word_size=4, bitcell_bl="bl0", bitcell_br="br0")
|
||||
self.local_check(a)
|
||||
|
||||
debug.info(1, "Testing sample for 8-way column_mux_array in multi-port (outermost connections)")
|
||||
a = single_level_column_mux_array.single_level_column_mux_array(columns=32, word_size=4, bitcell_bl="bl2", bitcell_br="br2")
|
||||
a = single_level_column_mux_array.single_level_column_mux_array(name="mux7", columns=32, word_size=4, bitcell_bl="bl2", bitcell_br="br2")
|
||||
self.local_check(a)
|
||||
|
||||
globals.end_openram()
|
||||
|
||||
@@ -10,17 +10,17 @@ sys.path.append(os.path.join(sys.path[0],".."))
|
||||
import globals
|
||||
from globals import OPTS
|
||||
import debug
|
||||
from sram_factory import factory
|
||||
|
||||
class precharge_test(openram_test):
|
||||
|
||||
def runTest(self):
|
||||
globals.init_openram("config_20_{0}".format(OPTS.tech_name))
|
||||
import precharge_array
|
||||
import tech
|
||||
|
||||
# check precharge array in single port
|
||||
debug.info(2, "Checking 3 column precharge")
|
||||
pc = precharge_array.precharge_array(columns=3)
|
||||
pc = precharge_array.precharge_array(name="pre1", columns=3)
|
||||
self.local_check(pc)
|
||||
|
||||
# check precharge array in multi-port
|
||||
@@ -28,17 +28,18 @@ class precharge_test(openram_test):
|
||||
OPTS.num_rw_ports = 1
|
||||
OPTS.num_r_ports = 1
|
||||
OPTS.num_w_ports = 0
|
||||
|
||||
|
||||
factory.reset()
|
||||
debug.info(2, "Checking 3 column precharge array for 1RW/1R bitcell")
|
||||
pc = precharge_array.precharge_array(columns=3, bitcell_bl="bl0", bitcell_br="br0")
|
||||
pc = precharge_array.precharge_array(name="pre2", columns=3, bitcell_bl="bl0", bitcell_br="br0")
|
||||
self.local_check(pc)
|
||||
|
||||
# debug.info(2, "Checking 3 column precharge array for pbitcell (innermost connections)")
|
||||
# pc = precharge_array.precharge_array(columns=3, bitcell_bl="bl0", bitcell_br="br0")
|
||||
# pc = precharge_array.precharge_array(name="pre3", columns=3, bitcell_bl="bl0", bitcell_br="br0")
|
||||
# self.local_check(pc)
|
||||
|
||||
# debug.info(2, "Checking 3 column precharge array for pbitcell (outermost connections)")
|
||||
# pc = precharge_array.precharge_array(columns=3, bitcell_bl="bl2", bitcell_br="br2")
|
||||
# pc = precharge_array.precharge_array(name="pre4", columns=3, bitcell_bl="bl2", bitcell_br="br2")
|
||||
# self.local_check(pc)
|
||||
|
||||
globals.end_openram()
|
||||
|
||||
@@ -10,6 +10,7 @@ sys.path.append(os.path.join(sys.path[0],".."))
|
||||
import globals
|
||||
from globals import OPTS
|
||||
import debug
|
||||
from sram_factory import factory
|
||||
|
||||
#@unittest.skip("SKIPPING 04_driver_test")
|
||||
|
||||
@@ -18,11 +19,10 @@ class wordline_driver_test(openram_test):
|
||||
def runTest(self):
|
||||
globals.init_openram("config_20_{0}".format(OPTS.tech_name))
|
||||
import wordline_driver
|
||||
import tech
|
||||
|
||||
# check wordline driver for single port
|
||||
debug.info(2, "Checking driver")
|
||||
tx = wordline_driver.wordline_driver(rows=8)
|
||||
tx = wordline_driver.wordline_driver(name="wld1", rows=8)
|
||||
self.local_check(tx)
|
||||
|
||||
# check wordline driver for multi-port
|
||||
@@ -30,9 +30,10 @@ class wordline_driver_test(openram_test):
|
||||
OPTS.num_rw_ports = 1
|
||||
OPTS.num_w_ports = 0
|
||||
OPTS.num_r_ports = 0
|
||||
|
||||
|
||||
factory.reset()
|
||||
debug.info(2, "Checking driver (multi-port case)")
|
||||
tx = wordline_driver.wordline_driver(rows=8)
|
||||
tx = wordline_driver.wordline_driver(name="wld2", rows=8)
|
||||
self.local_check(tx)
|
||||
|
||||
globals.end_openram()
|
||||
|
||||
@@ -10,6 +10,7 @@ sys.path.append(os.path.join(sys.path[0],".."))
|
||||
import globals
|
||||
from globals import OPTS
|
||||
import debug
|
||||
from sram_factory import factory
|
||||
|
||||
class sense_amp_test(openram_test):
|
||||
|
||||
@@ -19,11 +20,11 @@ class sense_amp_test(openram_test):
|
||||
|
||||
# check sense amp array for single port
|
||||
debug.info(2, "Testing sense_amp_array for word_size=4, words_per_row=2")
|
||||
a = sense_amp_array.sense_amp_array(word_size=4, words_per_row=2)
|
||||
a = sense_amp_array.sense_amp_array(name="sa1", word_size=4, words_per_row=2)
|
||||
self.local_check(a)
|
||||
|
||||
debug.info(2, "Testing sense_amp_array for word_size=4, words_per_row=4")
|
||||
a = sense_amp_array.sense_amp_array(word_size=4, words_per_row=4)
|
||||
a = sense_amp_array.sense_amp_array(name="sa2", word_size=4, words_per_row=4)
|
||||
self.local_check(a)
|
||||
|
||||
# check sense amp array for multi-port
|
||||
@@ -31,13 +32,14 @@ class sense_amp_test(openram_test):
|
||||
OPTS.num_rw_ports = 1
|
||||
OPTS.num_w_ports = 0
|
||||
OPTS.num_r_ports = 0
|
||||
|
||||
|
||||
factory.reset()
|
||||
debug.info(2, "Testing sense_amp_array for word_size=4, words_per_row=2 (multi-port case)")
|
||||
a = sense_amp_array.sense_amp_array(word_size=4, words_per_row=2)
|
||||
a = sense_amp_array.sense_amp_array(name="sa3", word_size=4, words_per_row=2)
|
||||
self.local_check(a)
|
||||
|
||||
debug.info(2, "Testing sense_amp_array for word_size=4, words_per_row=4 (multi-port case)")
|
||||
a = sense_amp_array.sense_amp_array(word_size=4, words_per_row=4)
|
||||
a = sense_amp_array.sense_amp_array(name="sa4", word_size=4, words_per_row=4)
|
||||
self.local_check(a)
|
||||
|
||||
globals.end_openram()
|
||||
|
||||
@@ -10,6 +10,7 @@ sys.path.append(os.path.join(sys.path[0],".."))
|
||||
import globals
|
||||
from globals import OPTS
|
||||
import debug
|
||||
from sram_factory import factory
|
||||
|
||||
class write_driver_test(openram_test):
|
||||
|
||||
@@ -19,11 +20,11 @@ class write_driver_test(openram_test):
|
||||
|
||||
# check write driver array for single port
|
||||
debug.info(2, "Testing write_driver_array for columns=8, word_size=8")
|
||||
a = write_driver_array.write_driver_array(columns=8, word_size=8)
|
||||
a = write_driver_array.write_driver_array(name="wd1", columns=8, word_size=8)
|
||||
self.local_check(a)
|
||||
|
||||
debug.info(2, "Testing write_driver_array for columns=16, word_size=8")
|
||||
a = write_driver_array.write_driver_array(columns=16, word_size=8)
|
||||
a = write_driver_array.write_driver_array(name="wd2", columns=16, word_size=8)
|
||||
self.local_check(a)
|
||||
|
||||
# check write driver array for multi-port
|
||||
@@ -31,13 +32,14 @@ class write_driver_test(openram_test):
|
||||
OPTS.num_rw_ports = 1
|
||||
OPTS.num_w_ports = 0
|
||||
OPTS.num_r_ports = 0
|
||||
|
||||
|
||||
factory.reset()
|
||||
debug.info(2, "Testing write_driver_array for columns=8, word_size=8 (multi-port case)")
|
||||
a = write_driver_array.write_driver_array(columns=8, word_size=8)
|
||||
a = write_driver_array.write_driver_array(name="wd3", columns=8, word_size=8)
|
||||
self.local_check(a)
|
||||
|
||||
debug.info(2, "Testing write_driver_array for columns=16, word_size=8 (multi-port case)")
|
||||
a = write_driver_array.write_driver_array(columns=16, word_size=8)
|
||||
a = write_driver_array.write_driver_array(name="wd4", columns=16, word_size=8)
|
||||
self.local_check(a)
|
||||
|
||||
globals.end_openram()
|
||||
|
||||
@@ -18,7 +18,7 @@ class delay_chain_test(openram_test):
|
||||
import delay_chain
|
||||
|
||||
debug.info(2, "Testing delay_chain")
|
||||
a = delay_chain.delay_chain(fanout_list=[4, 4, 4, 4])
|
||||
a = delay_chain.delay_chain(name="dc", fanout_list=[4, 4, 4, 4])
|
||||
self.local_check(a)
|
||||
|
||||
globals.end_openram()
|
||||
|
||||
@@ -10,6 +10,7 @@ sys.path.append(os.path.join(sys.path[0],".."))
|
||||
import globals
|
||||
from globals import OPTS
|
||||
import debug
|
||||
from sram_factory import factory
|
||||
|
||||
class replica_bitline_multiport_test(openram_test):
|
||||
|
||||
@@ -26,9 +27,10 @@ class replica_bitline_multiport_test(openram_test):
|
||||
OPTS.num_rw_ports = 1
|
||||
OPTS.num_r_ports = 1
|
||||
OPTS.num_w_ports = 0
|
||||
|
||||
|
||||
factory.reset()
|
||||
debug.info(2, "Testing 1rw 1r RBL with {0} FO4 stages, {1} rows".format(stages,rows))
|
||||
a = replica_bitline.replica_bitline(stages*[fanout],rows)
|
||||
a = replica_bitline.replica_bitline(name="rbl1", delay_fanout_list=stages*[fanout], bitcell_loads=rows)
|
||||
self.local_check(a)
|
||||
|
||||
# check replica bitline in pbitcell multi-port
|
||||
@@ -38,16 +40,18 @@ class replica_bitline_multiport_test(openram_test):
|
||||
OPTS.num_w_ports = 0
|
||||
OPTS.num_r_ports = 0
|
||||
|
||||
factory.reset()
|
||||
debug.info(2, "Testing RBL pbitcell 1rw with {0} FO4 stages, {1} rows".format(stages,rows))
|
||||
a = replica_bitline.replica_bitline(stages*[fanout],rows)
|
||||
a = replica_bitline.replica_bitline(name="rbl2", delay_fanout_list=stages*[fanout], bitcell_loads=rows)
|
||||
self.local_check(a)
|
||||
|
||||
OPTS.num_rw_ports = 1
|
||||
OPTS.num_w_ports = 1
|
||||
OPTS.num_r_ports = 1
|
||||
|
||||
factory.reset()
|
||||
debug.info(2, "Testing RBL pbitcell 1rw 1w 1r with {0} FO4 stages, {1} rows".format(stages,rows))
|
||||
a = replica_bitline.replica_bitline(stages*[fanout],rows)
|
||||
a = replica_bitline.replica_bitline(name="rbl3", delay_fanout_list=stages*[fanout], bitcell_loads=rows)
|
||||
self.local_check(a)
|
||||
|
||||
globals.end_openram()
|
||||
|
||||
@@ -22,14 +22,14 @@ class replica_bitline_test(openram_test):
|
||||
fanout=4
|
||||
rows=13
|
||||
debug.info(2, "Testing RBL with {0} FO4 stages, {1} rows".format(stages,rows))
|
||||
a = replica_bitline.replica_bitline(stages*[fanout],rows)
|
||||
a = replica_bitline.replica_bitline(name="rbl1", delay_fanout_list=stages*[fanout], bitcell_loads=rows)
|
||||
self.local_check(a)
|
||||
#debug.error("Exiting...", 1)
|
||||
|
||||
stages=8
|
||||
rows=100
|
||||
debug.info(2, "Testing RBL with {0} FO4 stages, {1} rows".format(stages,rows))
|
||||
a = replica_bitline.replica_bitline(stages*[fanout],rows)
|
||||
a = replica_bitline.replica_bitline(name="rbl2", delay_fanout_list=stages*[fanout], bitcell_loads=rows)
|
||||
self.local_check(a)
|
||||
|
||||
|
||||
|
||||
@@ -10,15 +10,13 @@ sys.path.append(os.path.join(sys.path[0],".."))
|
||||
import globals
|
||||
from globals import OPTS
|
||||
import debug
|
||||
from sram_factory import factory
|
||||
|
||||
#@unittest.skip("SKIPPING 19_psingle_bank_test")
|
||||
class psingle_bank_test(openram_test):
|
||||
|
||||
def runTest(self):
|
||||
globals.init_openram("config_20_{0}".format(OPTS.tech_name))
|
||||
global verify
|
||||
import verify
|
||||
|
||||
from bank import bank
|
||||
from sram_config import sram_config
|
||||
OPTS.bitcell = "pbitcell"
|
||||
@@ -31,6 +29,7 @@ class psingle_bank_test(openram_test):
|
||||
num_words=16)
|
||||
|
||||
c.words_per_row=1
|
||||
factory.reset()
|
||||
c.recompute_sizes()
|
||||
debug.info(1, "No column mux")
|
||||
name = "bank1_{0}rw_{1}w_{2}r_single".format(OPTS.num_rw_ports, OPTS.num_w_ports, OPTS.num_r_ports)
|
||||
@@ -39,6 +38,7 @@ class psingle_bank_test(openram_test):
|
||||
|
||||
c.num_words=32
|
||||
c.words_per_row=2
|
||||
factory.reset()
|
||||
c.recompute_sizes()
|
||||
debug.info(1, "Two way column mux")
|
||||
name = "bank2_{0}rw_{1}w_{2}r_single".format(OPTS.num_rw_ports, OPTS.num_w_ports, OPTS.num_r_ports)
|
||||
@@ -47,6 +47,7 @@ class psingle_bank_test(openram_test):
|
||||
|
||||
c.num_words=64
|
||||
c.words_per_row=4
|
||||
factory.reset()
|
||||
c.recompute_sizes()
|
||||
debug.info(1, "Four way column mux")
|
||||
name = "bank3_{0}rw_{1}w_{2}r_single".format(OPTS.num_rw_ports, OPTS.num_w_ports, OPTS.num_r_ports)
|
||||
@@ -56,6 +57,7 @@ class psingle_bank_test(openram_test):
|
||||
c.word_size=2
|
||||
c.num_words=128
|
||||
c.words_per_row=8
|
||||
factory.reset()
|
||||
c.recompute_sizes()
|
||||
debug.info(1, "Four way column mux")
|
||||
name = "bank4_{0}rw_{1}w_{2}r_single".format(OPTS.num_rw_ports, OPTS.num_w_ports, OPTS.num_r_ports)
|
||||
|
||||
Reference in New Issue
Block a user