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https://github.com/VLSIDA/OpenRAM.git
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First draft of sram_factory code
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@@ -2,6 +2,7 @@ from math import log
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import design
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from tech import drc
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import debug
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from sram_factory import factory
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from vector import vector
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from globals import OPTS
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@@ -11,8 +12,8 @@ class write_driver_array(design.design):
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Dynamically generated write driver array of all bitlines.
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"""
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def __init__(self, columns, word_size):
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design.design.__init__(self, "write_driver_array")
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def __init__(self, name, columns, word_size):
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design.design.__init__(self, name)
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debug.info(1, "Creating {0}".format(self.name))
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self.columns = columns
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@@ -53,17 +54,12 @@ class write_driver_array(design.design):
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self.add_pin("gnd")
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def add_modules(self):
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from importlib import reload
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c = reload(__import__(OPTS.write_driver))
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self.mod_write_driver = getattr(c, OPTS.write_driver)
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self.driver = self.mod_write_driver("write_driver")
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self.driver = factory.create(module_type="write_driver")
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self.add_mod(self.driver)
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# This is just used for measurements,
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# so don't add the module
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c = reload(__import__(OPTS.bitcell))
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self.mod_bitcell = getattr(c, OPTS.bitcell)
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self.bitcell = self.mod_bitcell()
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self.bitcell = factory.create(module_type="bitcell")
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def create_write_array(self):
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self.driver_insts = {}
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