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https://github.com/VLSIDA/OpenRAM.git
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First draft of sram_factory code
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@@ -3,6 +3,7 @@ import design
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from tech import drc
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from math import log
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from vector import vector
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from sram_factory import factory
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from globals import OPTS
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class dff_array(design.design):
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@@ -38,10 +39,7 @@ class dff_array(design.design):
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self.DRC_LVS()
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def add_modules(self):
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from importlib import reload
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c = reload(__import__(OPTS.dff))
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self.mod_dff = getattr(c, OPTS.dff)
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self.dff = self.mod_dff("dff")
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self.dff = factory.create(module_type="dff")
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self.add_mod(self.dff)
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def add_pins(self):
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@@ -61,7 +59,7 @@ class dff_array(design.design):
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for col in range(self.columns):
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name = "dff_r{0}_c{1}".format(row,col)
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self.dff_insts[row,col]=self.add_inst(name=name,
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mod=self.dff)
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mod=self.dff)
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self.connect_inst([self.get_din_name(row,col),
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self.get_dout_name(row,col),
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"clk",
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@@ -162,4 +160,4 @@ class dff_array(design.design):
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"""Return the total capacitance (in relative units) that the clock is loaded by in the dff array"""
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dff_clk_cin = self.dff.get_clk_cin()
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total_cin = dff_clk_cin * self.rows * self.columns
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return total_cin
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return total_cin
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