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Remove via-to-via path width hack

This commit is contained in:
mrg 2020-12-01 13:27:32 -08:00
parent a5b5f7c22b
commit a31e0dab02
1 changed files with 5 additions and 3 deletions
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8
compiler/modules/hierarchical_predecode.py
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@ -268,9 +268,11 @@ class hierarchical_predecode(design.design):
height=via.mod.second_layer_height, height=via.mod.second_layer_height,
width=via.mod.second_layer_width) width=via.mod.second_layer_width)
if layer_props.hierarchical_predecode.vertical_supply: # This is a hack to fix via-to-via spacing issues, but it is currently
below_rail = vector(self.decode_rails[out_pin].cx(), y_offset - (self.cell_height / 2)) # causing its own DRC problems.
self.add_path(self.bus_layer, [rail_pos, below_rail], width=self.li_width + self.m1_enclose_mcon * 2) # if layer_props.hierarchical_predecode.vertical_supply:
# below_rail = vector(self.decode_rails[out_pin].cx(), y_offset - (self.cell_height / 2))
# self.add_path(self.bus_layer, [rail_pos, below_rail], width=self.li_width + self.m1_enclose_mcon * 2)
def route_and_to_rails(self): def route_and_to_rails(self):
# This 2D array defines the connection mapping # This 2D array defines the connection mapping