From a31e0dab028debbfd0902a35a422b42c69957edc Mon Sep 17 00:00:00 2001 From: mrg Date: Tue, 1 Dec 2020 13:27:32 -0800 Subject: [PATCH] Remove via-to-via path width hack --- compiler/modules/hierarchical_predecode.py | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-) diff --git a/compiler/modules/hierarchical_predecode.py b/compiler/modules/hierarchical_predecode.py index 9b5cab65..72fb2a6d 100644 --- a/compiler/modules/hierarchical_predecode.py +++ b/compiler/modules/hierarchical_predecode.py @@ -268,9 +268,11 @@ class hierarchical_predecode(design.design): height=via.mod.second_layer_height, width=via.mod.second_layer_width) - if layer_props.hierarchical_predecode.vertical_supply: - below_rail = vector(self.decode_rails[out_pin].cx(), y_offset - (self.cell_height / 2)) - self.add_path(self.bus_layer, [rail_pos, below_rail], width=self.li_width + self.m1_enclose_mcon * 2) + # This is a hack to fix via-to-via spacing issues, but it is currently + # causing its own DRC problems. + # if layer_props.hierarchical_predecode.vertical_supply: + # below_rail = vector(self.decode_rails[out_pin].cx(), y_offset - (self.cell_height / 2)) + # self.add_path(self.bus_layer, [rail_pos, below_rail], width=self.li_width + self.m1_enclose_mcon * 2) def route_and_to_rails(self): # This 2D array defines the connection mapping