mirror of https://github.com/VLSIDA/OpenRAM.git
Vertical gates need both well contacts.
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4b526f0d5f
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a305d788d7
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@ -32,7 +32,7 @@ class pand2(pgate.pgate):
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def create_modules(self):
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def create_modules(self):
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self.nand = factory.create(module_type="pnand2",
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self.nand = factory.create(module_type="pnand2",
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height=self.height,
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height=self.height,
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add_wells=False)
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add_wells=self.vertical)
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self.inv = factory.create(module_type="pdriver",
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self.inv = factory.create(module_type="pdriver",
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size_list=[self.size],
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size_list=[self.size],
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@ -34,7 +34,7 @@ class pand3(pgate.pgate):
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# Shield the cap, but have at least a stage effort of 4
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# Shield the cap, but have at least a stage effort of 4
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self.nand = factory.create(module_type="pnand3",
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self.nand = factory.create(module_type="pnand3",
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height=self.height,
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height=self.height,
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add_wells=False)
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add_wells=self.vertical)
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# Add the well tap to the inverter because when stacked
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# Add the well tap to the inverter because when stacked
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# vertically it is sometimes narrower
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# vertically it is sometimes narrower
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