From a305d788d7635b4536ea43e0b2486660a59e5682 Mon Sep 17 00:00:00 2001 From: mrg Date: Wed, 13 May 2020 16:54:35 -0700 Subject: [PATCH] Vertical gates need both well contacts. --- compiler/pgates/pand2.py | 2 +- compiler/pgates/pand3.py | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/compiler/pgates/pand2.py b/compiler/pgates/pand2.py index dfbdc3e7..41189876 100644 --- a/compiler/pgates/pand2.py +++ b/compiler/pgates/pand2.py @@ -32,7 +32,7 @@ class pand2(pgate.pgate): def create_modules(self): self.nand = factory.create(module_type="pnand2", height=self.height, - add_wells=False) + add_wells=self.vertical) self.inv = factory.create(module_type="pdriver", size_list=[self.size], diff --git a/compiler/pgates/pand3.py b/compiler/pgates/pand3.py index d7f0b00e..92429921 100644 --- a/compiler/pgates/pand3.py +++ b/compiler/pgates/pand3.py @@ -34,7 +34,7 @@ class pand3(pgate.pgate): # Shield the cap, but have at least a stage effort of 4 self.nand = factory.create(module_type="pnand3", height=self.height, - add_wells=False) + add_wells=self.vertical) # Add the well tap to the inverter because when stacked # vertically it is sometimes narrower