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https://github.com/VLSIDA/OpenRAM.git
synced 2026-09-03 00:08:18 +02:00
Fixed bug for more than 2 wmasks and changed test to test 4 wmasks.
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@@ -447,7 +447,7 @@ class port_data(design.design):
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inst1 = self.write_mask_and_array_inst
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inst2 = self.write_driver_array_inst
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i = 0
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loc = 0
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for bit in range(self.num_wmasks):
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# Bring write mask AND array output pin to port data level
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self.copy_layout_pin(inst1, "wmask_out_{0}".format(bit), "wdriver_sel_{0}".format(bit))
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@@ -459,13 +459,13 @@ class port_data(design.design):
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# the wdriver_sel_{} pin in the write driver AND array.
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spacing = 2*drc("metal2_to_metal2")
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if bit == 0:
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while (wmask_out_pin.lx() > inst2.get_pin("data_{0}".format(i)).rx()):
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i += 1
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length = inst2.get_pin("data_{0}".format(i)).rx() + spacing
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while (wmask_out_pin.lx() > inst2.get_pin("data_{0}".format(loc)).rx()):
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loc += 1
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length = inst2.get_pin("data_{0}".format(loc)).rx() + spacing
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else:
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i = i + ( bit*self.write_size )
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length = inst2.get_pin("data_{0}".format(i)).rx() + spacing
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next_loc = loc + ( bit*self.write_size )
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length = inst2.get_pin("data_{0}".format(next_loc)).rx() + spacing
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beg_pos = wmask_out_pin.center()
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middle_pos = vector(length,wmask_out_pin.cy())
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