mirror of https://github.com/VLSIDA/OpenRAM.git
Fixed method of determining inverter number.
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@ -48,11 +48,8 @@ class pdriver(pgate.pgate):
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self.num_inv = len(self.size_list)
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else:
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# find the number of stages
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c_prev = int(round(self.c_load/self.stage_effort))
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num_stages = 1
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while c_prev > 1: #stop when the first stage is 1
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c_prev = int(round(c_prev/self.stage_effort))
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num_stages+=1
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#c_load is a unit inverter fanout, not a capacitance so c_in=1
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num_stages = int(round(log(self.c_load)/log(4)))
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# find inv_num and compute sizes
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if self.neg_polarity:
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