diff --git a/technology/gf180/__init__.py b/technology/gf180mcu/__init__.py similarity index 86% rename from technology/gf180/__init__.py rename to technology/gf180mcu/__init__.py index 45e04451..10a3899a 100644 --- a/technology/gf180/__init__.py +++ b/technology/gf180mcu/__init__.py @@ -13,7 +13,7 @@ This type of setup script should be placed in the setup_scripts directory in the import sys import os -TECHNOLOGY = "gf180" +TECHNOLOGY = "gf180mcu" os.environ["MGC_TMPDIR"] = "/tmp" @@ -22,19 +22,19 @@ os.environ["MGC_TMPDIR"] = "/tmp" # OpenPDK needed for magicrc, tech file and spice models of transistors if 'PDK_ROOT' in os.environ: - open_pdks = os.path.join(os.environ['PDK_ROOT'], 'gf180', 'libs.tech') + open_pdks = os.path.join(os.environ['PDK_ROOT'], 'gf180mcuA', 'libs.tech') else: raise SystemError("Unable to find open_pdks tech file. Set PDK_ROOT.") # The ngspice models work with Xyce too now spice_model_dir = os.path.join(open_pdks, "ngspice") -gf180_lib_ngspice = os.path.join(open_pdks, "ngspice", "gf180.lib.spice") +gf180_lib_ngspice = os.path.join(open_pdks, "ngspice", "sm141064.ngspice") if not os.path.exists(gf180_lib_ngspice): raise SystemError("Did not find {} under {}".format(gf180_lib_ngspice, open_pdks)) os.environ["SPICE_MODEL_DIR"] = spice_model_dir open_pdks = os.path.abspath(open_pdks) -gf180_magicrc = os.path.join(open_pdks, 'magic', "gf180A.magicrc") +gf180_magicrc = os.path.join(open_pdks, 'magic', "gf180mcuA.magicrc") if not os.path.exists(gf180_magicrc): raise SystemError("Did not find {} under {}".format(gf180_magicrc, open_pdks)) os.environ["OPENRAM_MAGICRC"] = gf180_magicrc diff --git a/technology/gf180mcu/mag_lib/.magicrc b/technology/gf180mcu/mag_lib/.magicrc new file mode 100644 index 00000000..1fa2e18d --- /dev/null +++ b/technology/gf180mcu/mag_lib/.magicrc @@ -0,0 +1,69 @@ +### +### Source file TECHNAME.magicrc +### Process this file with the m4 processor +### +puts stdout "Sourcing design .magicrc for technology TECHNAME ..." + +# Put internal grid on 0.005 pitch. This is important to match vendor file +# input (as opposed to SCMOS-style layout. The default lambda grid is 0.05um). + +set scalefac [tech lambda] +if {[lindex $scalefac 1] < 10} { + scalegrid 1 10 +} + +# drc off +drc euclidean on +# Change this to a fixed number for repeatable behavior with GDS writes +# e.g., "random seed 12345" +catch {random seed} + +# Allow override of PDK path from environment variable PDK_ROOT +# "file nativename" guards against a local PDK_ROOT with "~" in the name +if {[catch {set PDK_ROOT [file nativename $env(PDK_ROOT)]}]} { + set PDK_ROOT STAGING_PATH +} + +# loading technology +tech load $PDK_ROOT/TECHNAME/MAGIC_CURRENT/TECHNAME.tech + +# load device generator +source $PDK_ROOT/TECHNAME/MAGIC_CURRENT/TECHNAME.tcl + +# load bind keys +# source $PDK_ROOT/TECHNAME/MAGIC_CURRENT/TECHNAME-BindKeys + +# set units to lambda grid +snap lambda + +# set gf180mcu standard power, ground, and substrate names +set VDD VDD +set GND VSS +set SUB VSUBS + +# Allow override of type of magic library views used, "mag" or "maglef", +# from environment variable MAGTYPE + +if {[catch {set MAGTYPE $env(MAGTYPE)}]} { + set MAGTYPE mag +} + +# add path to reference cells +if {[file isdir ${PDK_ROOT}/TECHNAME/libs.ref/${MAGTYPE}]} { + addpath ${PDK_ROOT}/TECHNAME/libs.ref/${MAGTYPE}/gf180mcu_fd_pr + addpath ${PDK_ROOT}/TECHNAME/libs.ref/${MAGTYPE}/gf180mcu_mcu7t5v0 + addpath ${PDK_ROOT}/TECHNAME/libs.ref/${MAGTYPE}/gf180mcu_mcu9t5v0 + addpath ${PDK_ROOT}/TECHNAME/libs.ref/${MAGTYPE}/gf180mcu_fd_io + addpath ${PDK_ROOT}/TECHNAME/libs.ref/${MAGTYPE}/gf180mcu_fd_ip_sram +} else { + addpath ${PDK_ROOT}/TECHNAME/libs.ref/gf180mcu_fd_pr/${MAGTYPE} + addpath ${PDK_ROOT}/TECHNAME/libs.ref/gf180mcu_fd_sc_mcu7t5v0/${MAGTYPE} + addpath ${PDK_ROOT}/TECHNAME/libs.ref/gf180mcu_fd_sc_mcu9t5v0/${MAGTYPE} + addpath ${PDK_ROOT}/TECHNAME/libs.ref/gf180mcu_fd_io/${MAGTYPE} + addpath ${PDK_ROOT}/TECHNAME/libs.ref/gf180mcu_fd_ip_sram/${MAGTYPE} +} + +# add path to IP from catalog. This procedure defined in the PDK script. +catch {magic::query_mylib_ip} +# add path to local IP from user design space. Defined in the PDK script. +catch {magic::query_my_projects} diff --git a/technology/gf180mcu/tech/.magicrc b/technology/gf180mcu/tech/.magicrc new file mode 100644 index 00000000..1fa2e18d --- /dev/null +++ b/technology/gf180mcu/tech/.magicrc @@ -0,0 +1,69 @@ +### +### Source file TECHNAME.magicrc +### Process this file with the m4 processor +### +puts stdout "Sourcing design .magicrc for technology TECHNAME ..." + +# Put internal grid on 0.005 pitch. This is important to match vendor file +# input (as opposed to SCMOS-style layout. The default lambda grid is 0.05um). + +set scalefac [tech lambda] +if {[lindex $scalefac 1] < 10} { + scalegrid 1 10 +} + +# drc off +drc euclidean on +# Change this to a fixed number for repeatable behavior with GDS writes +# e.g., "random seed 12345" +catch {random seed} + +# Allow override of PDK path from environment variable PDK_ROOT +# "file nativename" guards against a local PDK_ROOT with "~" in the name +if {[catch {set PDK_ROOT [file nativename $env(PDK_ROOT)]}]} { + set PDK_ROOT STAGING_PATH +} + +# loading technology +tech load $PDK_ROOT/TECHNAME/MAGIC_CURRENT/TECHNAME.tech + +# load device generator +source $PDK_ROOT/TECHNAME/MAGIC_CURRENT/TECHNAME.tcl + +# load bind keys +# source $PDK_ROOT/TECHNAME/MAGIC_CURRENT/TECHNAME-BindKeys + +# set units to lambda grid +snap lambda + +# set gf180mcu standard power, ground, and substrate names +set VDD VDD +set GND VSS +set SUB VSUBS + +# Allow override of type of magic library views used, "mag" or "maglef", +# from environment variable MAGTYPE + +if {[catch {set MAGTYPE $env(MAGTYPE)}]} { + set MAGTYPE mag +} + +# add path to reference cells +if {[file isdir ${PDK_ROOT}/TECHNAME/libs.ref/${MAGTYPE}]} { + addpath ${PDK_ROOT}/TECHNAME/libs.ref/${MAGTYPE}/gf180mcu_fd_pr + addpath ${PDK_ROOT}/TECHNAME/libs.ref/${MAGTYPE}/gf180mcu_mcu7t5v0 + addpath ${PDK_ROOT}/TECHNAME/libs.ref/${MAGTYPE}/gf180mcu_mcu9t5v0 + addpath ${PDK_ROOT}/TECHNAME/libs.ref/${MAGTYPE}/gf180mcu_fd_io + addpath ${PDK_ROOT}/TECHNAME/libs.ref/${MAGTYPE}/gf180mcu_fd_ip_sram +} else { + addpath ${PDK_ROOT}/TECHNAME/libs.ref/gf180mcu_fd_pr/${MAGTYPE} + addpath ${PDK_ROOT}/TECHNAME/libs.ref/gf180mcu_fd_sc_mcu7t5v0/${MAGTYPE} + addpath ${PDK_ROOT}/TECHNAME/libs.ref/gf180mcu_fd_sc_mcu9t5v0/${MAGTYPE} + addpath ${PDK_ROOT}/TECHNAME/libs.ref/gf180mcu_fd_io/${MAGTYPE} + addpath ${PDK_ROOT}/TECHNAME/libs.ref/gf180mcu_fd_ip_sram/${MAGTYPE} +} + +# add path to IP from catalog. This procedure defined in the PDK script. +catch {magic::query_mylib_ip} +# add path to local IP from user design space. Defined in the PDK script. +catch {magic::query_my_projects} diff --git a/technology/gf180mcu/tech/__init__.py b/technology/gf180mcu/tech/__init__.py new file mode 100644 index 00000000..c6bd5798 --- /dev/null +++ b/technology/gf180mcu/tech/__init__.py @@ -0,0 +1,12 @@ +#!/usr/bin/env python3 +# See LICENSE for licensing information. +# +# Copyright (c) 2016-2022 Regents of the University of California +# All rights reserved. +# + +""" +Import tech specific modules. +""" + +from .tech import * diff --git a/technology/gf180mcu/tech/gf180mcu.lym b/technology/gf180mcu/tech/gf180mcu.lym new file mode 100644 index 00000000..c819e2ea --- /dev/null +++ b/technology/gf180mcu/tech/gf180mcu.lym @@ -0,0 +1,49 @@ + + + + + + pymacros + + + + true + false + + false + + + python + + + +import sys +import os + +technology_macros_path = os.path.dirname(os.path.abspath(__file__)) +sys.path.insert(0, technology_macros_path) + +from cells import gf180mcu + +# Instantiate and register the library +gf180mcu() + +print("## gf180mcu PDK Pcells loaded.") +print(sys.path) + + + diff --git a/technology/gf180mcu/tech/gf180mcu.lyp b/technology/gf180mcu/tech/gf180mcu.lyp new file mode 100644 index 00000000..1b996571 --- /dev/null +++ b/technology/gf180mcu/tech/gf180mcu.lyp @@ -0,0 +1,2008 @@ + + + + + #55ce57 + #55ce57 + 0 + 0 + I3 + + true + false + false + 1 + false + false + 0 + + 1/222@1 + + + #661a48 + #661a48 + 0 + 0 + I3 + + true + false + false + 1 + false + false + 0 + + pass_mk 2/222@1 + + + #7c6078 + #7c6078 + 0 + 0 + I3 + + true + false + false + 1 + false + false + 0 + + fail_mk 3/222@1 + + + #f26f6c + #f26f6c + 0 + 0 + I3 + + true + false + false + 1 + false + false + 0 + + polygon_mk 4/222@1 + + + #324416 + #324416 + 0 + 0 + I3 + + true + false + false + 1 + false + false + 0 + + 5/222@1 + + + #3acb88 + #3acb88 + 0 + 0 + I3 + + true + false + false + 1 + false + false + 0 + + violation_mk 6/222@1 + + + #5a68c2 + #5a68c2 + 0 + 0 + I3 + + true + false + false + 1 + false + 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false + 1 + false + false + 0 + + DEV_WF_MK 128/17@1 + + + #8e3415 + #8e3415 + 0 + 0 + I9 + + true + true + false + 1 + false + false + 0 + + Metal1_BLK 34/5@1 + + + #47649f + #47649f + 0 + 0 + I5 + + true + true + false + 1 + false + false + 0 + + Metal2_BLK 36/5@1 + + + #3bf37a + #3bf37a + 0 + 0 + I9 + + true + true + false + 1 + false + false + 0 + + Metal3_BLK 42/5@1 + + + #678619 + #678619 + 0 + 0 + I5 + + true + true + false + 1 + false + false + 0 + + Metal4_BLK 46/5@1 + + + #44fa82 + #44fa82 + 0 + 0 + I9 + + true + true + false + 1 + false + false + 0 + + Metal5_BLK 81/5@1 + + + #614b6a + #614b6a + 0 + 0 + I5 + + true + true + false + 1 + false + false + 0 + + MetalT_BLK 53/5@1 + + + #d9f817 + #d9f817 + 0 + 0 + I9 + + true + true + false + 1 + false + false + 0 + + PR_bndry 0/0@1 + + + #0bdfb7 + #0bdfb7 + 0 + 0 + I5 + + true + true + false + 1 + false + false + 0 + + MDIODE 116/5@1 + + + #658af3 + #658af3 + 0 + 0 + I9 + + true + true + false + 1 + false + false + 0 + + Metal1_Res 110/11@1 + + + #e9465c + #e9465c + 0 + 0 + I5 + + true + true + false + 1 + false + false + 0 + + Metal2_Res 110/12@1 + + + #ba3263 + #ba3263 + 0 + 0 + I9 + + true + true + false + 1 + false + false + 0 + + Metal3_Res 110/13@1 + + + #ddeef3 + #ddeef3 + 0 + 0 + I5 + + true + true + false + 1 + false + false + 0 + + Metal4_Res 110/14@1 + + + #004676 + #004676 + 0 + 0 + I9 + + true + true + false + 1 + false + false + 0 + + Metal5_Res 110/15@1 + + + #e4b00d + #e4b00d + 0 + 0 + I5 + + true + true + false + 1 + false + false + 0 + + Metal6_Res 110/16@1 + + + #edeb06 + #edeb06 + 0 + 0 + I9 + + true + true + false + 1 + false + false + 0 + + Border 63/0@1 + + + diff --git a/technology/gf180mcu/tech/gf180mcu.lyt b/technology/gf180mcu/tech/gf180mcu.lyt new file mode 100644 index 00000000..c5959dcd --- /dev/null +++ b/technology/gf180mcu/tech/gf180mcu.lyt @@ -0,0 +1,233 @@ + + + + gf180mcu + GLOBALFOUNDRIES 0.18UM 3.3V/(5V)6V MCU TECHNOLOGY + + 0.001 + + $PDK_ROOT/$PDK/libs.tech/klayout + gf180mcu.lyp + true + + + 1 + true + true + + + true + layer_map() + true + true + + + true + layer_map() + 0.001 + true + #1 + true + #1 + false + #1 + true + OUTLINE + true + PLACEMENT_BLK + true + REGIONS + true + + 0 + true + .PIN + 2 + true + .PIN + 2 + true + .FILL + 5 + true + .OBS + 3 + true + .BLK + 4 + true + .LABEL + 1 + true + .LABEL + 1 + true + + 0 + true + + 0 + VIA_ + true + default + false + + + + false + true + true + 64 + 0 + 1 + 0 + DATA + 0 + 0 + BORDER + layer_map() + true + + + 0.001 + 1 + 100 + 100 + 0 + 0 + 0 + false + false + false + true + layer_map() + + + 0 + 0.001 + layer_map() + true + false + + + 1 + 0.001 + layer_map() + true + false + true + + + + + + + true + false + false + false + false + false + 8000 + 32000 + LIB + + + 2 + false + false + 1 + * + false + + + 0 + + + false + false + + + 0 + + true + + + + # Provide z stack information here +# +# Each line is one layer. The specification consists of a layer specification, a colon and arguments. +# The arguments are named (like "x=...") or in serial. Parameters are separated by comma or blanks. +# Named arguments are: +# +# zstart The lower z position of the extruded layer in µm +# zstop The upper z position of the extruded layer in µm +# height The height of the extruded layer in µm +# +# 'height', 'zstart' and 'zstop' can be used in any combination. If no value is given for 'zstart', +# the upper level of the previous layer will be used. +# +# If a single unnamed parameter is given, it corresponds to 'height'. Two parameters correspond to +# 'zstart' and 'zstop'. +# +# Examples: +# 1: 0.5 1.5 # extrude layer 1/0 from 0.5 to 1.5 vertically +# 1/0: 0.5 1.5 # same with explicit datatype +# 1: zstop=1.5, zstart=0.5 # same with named parameters +# 1: height=1.0, zstop=1.5 # same with z stop minus height +# 1: 1.0 zstop=1.5 # same with height as unnamed parameter +# +# VARIABLES +# +# You can declare variables with: +# var name = value +# +# You can use variables inside numeric expressions. +# Example: +# var hmetal = 0.48 +# 7/0: 0.5 0.5+hmetal*2 # 2x thick metal +# +# You cannot use variables inside layer specifications currently. +# +# CONDITIONALS +# +# You can enable or disable branches of the table using 'if', 'else', 'elseif' and 'end': +# Example: +# var thick_m1 = true +# if thickm1 +# 1: 0.5 1.5 +# else +# 1: 0.5 1.2 +# end + + + + + 30/0,33/0,Metal1 + Metal1,35/0,Metal2 + Metal2,38/0,Metal3 + Metal3,40/0,Metal4 + Metal4,41/0,Metal5 + Metal5,82/0,53/0 + + Metal1='34/0+34/10' + Metal2='36/0+36/10' + Metal3='42/0+42/10' + Metal4='46/0+46/10' + Metal5='81/0+81/10' + + diff --git a/technology/gf180/tech/tech.py b/technology/gf180mcu/tech/tech.py similarity index 68% rename from technology/gf180/tech/tech.py rename to technology/gf180mcu/tech/tech.py index 9c946aee..66e9d3a0 100644 --- a/technology/gf180/tech/tech.py +++ b/technology/gf180mcu/tech/tech.py @@ -132,6 +132,7 @@ layer_names = {} layer_names["active"] = "active" layer_names["pwell"] = "pwell" layer_names["nwell"] = "nwell" +layer_names["dnwell"] = "dnwell" layer_names["nimplant"]= "nimplant" layer_names["pimplant"]= "pimplant" layer_names["poly"] = "poly" @@ -153,225 +154,218 @@ layer_names["boundary"]= "boundary" # technology parameter parameter={} -# difftap.2b + parameter["min_tx_size"] = 0.250 parameter["beta"] = 3 -parameter["6T_inv_nmos_size"] = 0.205 -parameter["6T_inv_pmos_size"] = 0.09 -parameter["6T_access_size"] = 0.135 - +parameter["6T_inv_nmos_size"] = 0.6 +parameter["6T_inv_pmos_size"] = 0.95 +parameter["6T_access_size"] = 0.6 drc = d.design_rules("gf180") # grid size drc["grid"] = 0.005 -# minwidth_tx with contact (no dog bone transistors) -# difftap.2b -drc["minwidth_tx"] = 0.360 -drc["minlength_channel"] = 0.150 +drc["minwidth_tx"] = 0.28 +#drc["minlength_channel"] = 0.150 + +drc["pwell_to_nwell"] = 0 # assuming same potential -drc["pwell_to_nwell"] = 0 -# nwell.1 Minimum width of nwell/pwell drc.add_layer("nwell", - width=0.840, - spacing=1.270) + width=0.86, + spacing=0.6) + +drc.add_layer("pwell", + width=0.74, # 0.6 for 1.5v + spacing=0.86) # equal potential 1.7 otherwise -# poly.1a Minimum width of poly -# poly.2 Minimum spacing of poly AND active drc.add_layer("poly", - width=0.150, - spacing=0.210) + width=0.18, + spacing=0.24) # poly.8 -drc["poly_extend_active"] = 0.13 +#drc["poly_extend_active"] = 0.13 # Not a rule -drc["poly_to_contact"] = 0 +#drc["poly_to_contact"] = 0 # poly.7 Minimum enclosure of active around gate -drc["active_enclose_gate"] = 0.075 +#drc["active_enclose_gate"] = 0.075 # poly.4 Minimum spacing of field poly to active -drc["poly_to_active"] = 0.075 +#drc["poly_to_active"] = 0.075 # poly.2 Minimum spacing of field poly -drc["poly_to_field_poly"] = 0.210 +#drc["poly_to_field_poly"] = 0.210 -# difftap.1 Minimum width of active -# difftap.3 Minimum spacing of active drc.add_layer("active", - width=0.150, - spacing=0.270) -# difftap.8 + width=0.22, + spacing=0.280) + +drc.add_enclosure("dnwell", + layer="pwell", + enclosure=2.5, + extension=2.5) + drc.add_enclosure("nwell", layer="active", - enclosure=0.18, - extension=0.18) + enclosure=0.43, + extension=0.6) -# nsd/psd.5a -drc.add_enclosure("implant", +drc.add_enclosure("pwell", layer="active", - enclosure=0.125) + enclosure=0.43, + extension=0.6) +# nsd/psd.5a +#drc.add_enclosure("implant", +# layer="active", +# enclosure=0.125) # Same as active enclosure? -drc["implant_to_contact"] = 0.070 +#drc["implant_to_contact"] = 0.070 # nsd/psd.1 nsd/psd.2 -drc.add_layer("implant", - width=0.380, - spacing=0.380, - area=0.265) +#drc.add_layer("implant", +# width=0.380, +# spacing=0.380, +# area=0.265) # licon.1, licon.2 -drc.add_layer("contact", - width=0.170, - spacing=0.170) +#drc.add_layer("contact", +# width=0.170, +# spacing=0.170) # licon.5c (0.06 extension), (licon.7 for extension) -drc.add_enclosure("active", - layer="contact", - enclosure=0.040, - extension=0.060) +#drc.add_enclosure("active", +# layer="contact", +# enclosure=0.040, +# extension=0.060) # licon.7 -drc["tap_extend_contact"] = 0.120 +#drc["tap_extend_contact"] = 0.120 # licon.8 Minimum enclosure of poly around contact -drc.add_enclosure("poly", - layer="contact", - enclosure=0.08, - extension=0.08) +#drc.add_enclosure("poly", +# layer="contact", +# enclosure=0.08, +# extension=0.08) # licon.11a -drc["active_contact_to_gate"] = 0.050 +#drc["active_contact_to_gate"] = 0.050 # npc.4 > licon.14 0.19 > licon.11a -drc["poly_contact_to_gate"] = 0.270 +#drc["poly_contact_to_gate"] = 0.270 # licon.15 -drc["npc_enclose_poly"] = 0.1 +#drc["npc_enclose_poly"] = 0.1 # li.1, li.3 -drc.add_layer("li", - width=0.170, - spacing=0.170) +#drc.add_layer("li", +# width=0.170, +# spacing=0.170) # licon.5 -drc.add_enclosure("li", - layer="contact", - enclosure=0, - extension=0.080) +#drc.add_enclosure("li", +# layer="contact", +# enclosure=0, +# extension=0.080) -drc.add_enclosure("li", - layer="mcon", - enclosure=0, - extension=0.080) +#drc.add_enclosure("li", +# layer="mcon", +# enclosure=0, +# extension=0.080) # mcon.1, mcon.2 -drc.add_layer("mcon", - width=0.170, - spacing=0.210) +#drc.add_layer("mcon", +# width=0.170, +# spacing=0.210) -# m1.1 Minimum width of metal1 -# m1.2 Minimum spacing of metal1 -# m1.6 Minimum area of metal1 drc.add_layer("m1", - width=0.140, - spacing=0.140, - area=0.083) + width=0.23, + spacing=0.23, + area=0.1444) # m1.4 Minimum enclosure of metal1 # m1.5 Minimum enclosure around contact on two opposite sides -drc.add_enclosure("m1", - layer="mcon", - enclosure=0.030, - extension=0.060) +#drc.add_enclosure("m1", +# layer="mcon", +# enclosure=0.030, +# extension=0.060) # via.4a Minimum enclosure around via1 # via.5a Minimum enclosure around via1 on two opposite sides -drc.add_enclosure("m1", - layer="via1", - enclosure=0.055, - extension=0.085) +#drc.add_enclosure("m1", +# layer="via1", +# enclosure=0.055, +# extension=0.085) # via.1a Minimum width of via1 # via.2 Minimum spacing of via1 -drc.add_layer("via1", - width=0.150, - spacing=0.170) +#drc.add_layer("via1", +# width=0.150, +# spacing=0.170) -# m2.1 Minimum width of intermediate metal -# m2.2 Minimum spacing of intermediate metal -# m2.6 Minimum area of metal2 drc.add_layer("m2", - width=0.140, - spacing=0.140, - area=0.0676) + width=0.28, + spacing=0.28, + area=0.1444) # m2.4 Minimum enclosure around via1 # m2.5 Minimum enclosure around via1 on two opposite sides -drc.add_enclosure("m2", - layer="via1", - enclosure=0.055, - extension=0.085) +#drc.add_enclosure("m2", +# layer="via1", +# enclosure=0.055, +# extension=0.085) # via2.4 Minimum enclosure around via2 # via2.5 Minimum enclosure around via2 on two opposite sides -drc.add_enclosure("m2", - layer="via2", - enclosure=0.040, - extension=0.085) +#drc.add_enclosure("m2", +# layer="via2", +# enclosure=0.040, +# extension=0.085) # via2.1a Minimum width of Via2 # via2.2 Minimum spacing of Via2 -drc.add_layer("via2", - width=0.200, - spacing=0.200) +#drc.add_layer("via2", +# width=0.200, +# spacing=0.200) -# m3.1 Minimum width of metal3 -# m3.2 Minimum spacing of metal3 -# m3.6 Minimum area of metal3 drc.add_layer("m3", - width=0.300, - spacing=0.300, - area=0.240) + width=0.28, + spacing=0.28, + area=0.1444) # m3.4 Minimum enclosure around via2 -drc.add_enclosure("m3", - layer="via2", - enclosure=0.065) +#drc.add_enclosure("m3", +# layer="via2", +# enclosure=0.065) # via3.4 Minimum enclosure around via3 # via3.5 Minimum enclosure around via3 on two opposite sides -drc.add_enclosure("m3", - layer="via3", - enclosure=0.060, - extension=0.090) +#drc.add_enclosure("m3", +# layer="via3", +# enclosure=0.060, +# extension=0.090) # via3.1 Minimum width of Via3 # via3.2 Minimum spacing of Via3 -drc.add_layer("via3", - width=0.200, - spacing=0.200) +#drc.add_layer("via3", +# width=0.200, +# spacing=0.200) -# m4.1 Minimum width of metal4 -# m4.2 Minimum spacing of metal4 -# m4.7 Minimum area of metal4 drc.add_layer("m4", - width=0.300, - spacing=0.300, - area=0.240) + width=0.28, + spacing=0.28, + area=0.1444) # m4.3 Minimum enclosure around via3 -drc.add_enclosure("m4", - layer="via3", - enclosure=0.065) -# FIXME: Wrong rule m4.3 Minimum enclosure around via3 -drc.add_enclosure("m4", - layer="via4", - enclosure=0.060) +#drc.add_enclosure("m4", +# layer="via3", +# enclosure=0.065) + +#drc.add_enclosure("m4", +# layer="via4", +# enclosure=0.060) # via4.1 Minimum width of Via4 # via4.2 Minimum spacing of Via4 -drc.add_layer("via4", - width=0.800, - spacing=0.800) +#drc.add_layer("via4", +# width=0.800, +# spacing=0.800) -# FIXME: Wrong rules # m5.1 Minimum width of metal5 # m5.2 Minimum spacing of metal5 # m5.7 Minimum area of metal5 -drc.add_layer("m5", - width=1.600, - spacing=1.600, - area=4.000) +#drc.add_layer("m5", +# width=1.600, +# spacing=1.600, +# area=4.000) # m5.3 Minimum enclosure around via4 -drc.add_enclosure("m5", - layer="via4", - enclosure=0.310) +#drc.add_enclosure("m5", +# layer="via4", +# enclosure=0.310) @@ -439,16 +433,16 @@ parameter["bitcell_drain_cap"] = 0.1 # In Femto-Farad, approximation of d # Technology Tool Preferences ################################################### -if use_calibre: - drc_name = "calibre" - lvs_name = "calibre" - pex_name = "calibre" -elif use_klayout: - drc_name = "klayout" - lvs_name = "klayout" - pex_name = "klayout" -else: - drc_name = "magic" - lvs_name = "netgen" - pex_name = "magic" +#if use_calibre: +# drc_name = "calibre" +# lvs_name = "calibre" +# pex_name = "calibre" +#if use_klayout: +# drc_name = "klayout" +# lvs_name = "klayout" +# pex_name = "klayout" +#else: +drc_name = "magic" +lvs_name = "netgen" +pex_name = "magic"