diff --git a/compiler/bitcells/col_cap_bitcell_1rw_1r.py b/compiler/bitcells/col_cap_bitcell_1rw_1r.py
index 119d51f8..1f2a30d0 100644
--- a/compiler/bitcells/col_cap_bitcell_1rw_1r.py
+++ b/compiler/bitcells/col_cap_bitcell_1rw_1r.py
@@ -22,9 +22,11 @@ class col_cap_bitcell_1rw_1r(bitcell_base.bitcell_base):
     type_list = ["OUTPUT", "OUTPUT", "OUTPUT", "OUTPUT",
                  "POWER", "GROUND"]
 
-    def __init__(self, name="col_cap_cell_1rw_1r"):
+    def __init__(self, name="col_cap_cell_1rw_1r", cell_name=None):
+        if not cell_name:
+            cell_name = name
         # Ignore the name argument
-        bitcell_base.bitcell_base.__init__(self, name)
+        bitcell_base.bitcell_base.__init__(self, name, cell_name)
         debug.info(2, "Create col_cap bitcell 1rw+1r object")
 
         self.no_instances = True
diff --git a/compiler/bitcells/row_cap_bitcell_1rw_1r.py b/compiler/bitcells/row_cap_bitcell_1rw_1r.py
index fbe08a54..17de5d34 100644
--- a/compiler/bitcells/row_cap_bitcell_1rw_1r.py
+++ b/compiler/bitcells/row_cap_bitcell_1rw_1r.py
@@ -22,9 +22,10 @@ class row_cap_bitcell_1rw_1r(bitcell_base.bitcell_base):
                  props.bitcell.cell_1rw1r.pin.gnd]
     type_list = ["INPUT", "INPUT", "GROUND"]
 
-    def __init__(self, name="row_cap_cell_1rw_1r"):
-        # Ignore the name argument
-        bitcell_base.bitcell_base.__init__(self, name)
+    def __init__(self, name="row_cap_cell_1rw_1r", cell_name=None):
+        if not cell_name:
+            cell_name = name
+        bitcell_base.bitcell_base.__init__(self, name, cell_name)
         debug.info(2, "Create row_cap bitcell 1rw+1r object")
 
         self.no_instances = True