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https://github.com/VLSIDA/OpenRAM.git
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Removed L shaped routing from gnd contact to wordlines in replica bitline. Corrected slight DRC errors. Optimizations to pbitcell.
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@@ -222,9 +222,9 @@ class pbitcell(design.design):
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self.rowline_spacing = self.m1_space + contact.m1m2.width
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# spacing for vdd
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vdd_offset_well_constraint = self.well_enclose_active + 0.5*contact.well.width
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vdd_offset_metal1_constraint = max(inverter_pmos_contact_extension, 0) + self.m1_space + 0.5*contact.well.width
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self.vdd_offset = max(vdd_offset_well_constraint, vdd_offset_metal1_constraint)
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implant_constraint = max(inverter_pmos_contact_extension, 0) + 2*self.implant_enclose_active + 0.5*(contact.well.width - self.m1_width)
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metal1_constraint = max(inverter_pmos_contact_extension, 0) + self.m1_space
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self.vdd_offset = max(implant_constraint, metal1_constraint) + 0.5*self.m1_width
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# read port dimensions
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width_reduction = self.read_nmos.active_width - self.read_nmos.get_pin("D").cx()
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@@ -334,7 +334,7 @@ class pbitcell(design.design):
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layer="metal1",
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offset=self.gnd_position,
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width=self.width,
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height=contact.well.second_layer_width)
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height=self.m1_width)
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vdd_ypos = self.inverter_nmos_ypos + self.inverter_nmos.active_height + self.inverter_gap + self.inverter_pmos.active_height + self.vdd_offset
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self.vdd_position = vector(0, vdd_ypos)
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@@ -342,7 +342,7 @@ class pbitcell(design.design):
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layer="metal1",
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offset=self.vdd_position,
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width=self.width,
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height=contact.well.second_layer_width)
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height=self.m1_width)
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def create_readwrite_ports(self):
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"""
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@@ -933,8 +933,9 @@ class pbitcell(design.design):
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def route_rbc_short(self):
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""" route the short from Q_bar to gnd necessary for the replica bitcell """
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Q_bar_pos = self.inverter_pmos_right.get_pin("S").uc()
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vdd_pos = vector(Q_bar_pos.x, self.vdd_position.y)
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Q_bar_pos = self.inverter_pmos_right.get_pin("S").center()
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vdd_pos = self.inverter_pmos_right.get_pin("D").center()
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#vdd_pos = vector(Q_bar_pos.x, self.vdd_position.y)
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self.add_path("metal1", [Q_bar_pos, vdd_pos])
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