From a06a0975db0b242d81256df99a9ff2f73f6ad602 Mon Sep 17 00:00:00 2001
From: Michael Timothy Grimes <mtgrimes@mada0.SOE.UCSC.EDU>
Date: Thu, 18 Oct 2018 07:05:47 -0700
Subject: [PATCH] Removed L shaped routing from gnd contact to wordlines in
 replica bitline. Corrected slight DRC errors. Optimizations to pbitcell.

---
 compiler/modules/replica_bitline.py | 18 ++++++------------
 compiler/pgates/pbitcell.py         | 15 ++++++++-------
 2 files changed, 14 insertions(+), 19 deletions(-)

diff --git a/compiler/modules/replica_bitline.py b/compiler/modules/replica_bitline.py
index e84efcf1..bf635538 100644
--- a/compiler/modules/replica_bitline.py
+++ b/compiler/modules/replica_bitline.py
@@ -76,7 +76,6 @@ class replica_bitline(design.design):
         self.access_tx_offset = vector(-gap_width-self.access_tx.width-self.inv.width, 0.5*self.inv.height)
 
 
-
     def add_modules(self):
         """ Add the modules for later usage """
 
@@ -184,19 +183,14 @@ class replica_bitline(design.design):
             pin = self.rbl_inst.get_pin(wl)
 
             # Route the connection to the right so that it doesn't interfere with the cells
-            # Wordlines may be close to each other when tiled, so gnd connections are routed in opposite directions
-            if row % 2 == 0:
-                vertical_extension = vector(0, 1.5*drc["minwidth_metal1"] + 0.5*contact.m1m2.height)
-            else:
-                vertical_extension = vector(0, -1.5*drc["minwidth_metal1"] - 1.5*contact.m1m2.height)
-            
+            # Wordlines may be close to each other when tiled, so gnd connections are routed in opposite directions            
             pin_right = pin.rc()
-            pin_extension1 = pin_right + vector(self.m3_pitch,0)
-            pin_extension2 = pin_extension1 + vertical_extension
+            pin_extension = pin_right + vector(self.m3_pitch,0)
+
             if pin.layer != "metal1":
                 continue
-            self.add_path("metal1", [pin_right, pin_extension1, pin_extension2])
-            self.add_power_pin("gnd", pin_extension2)
+            self.add_path("metal1", [pin_right, pin_extension])
+            self.add_power_pin("gnd", pin_extension)
             
             # for multiport, need to short wordlines to each other so they all connect to gnd 
             wl_last = self.wl_list[self.total_ports-1]+"_{}".format(row)
@@ -280,7 +274,7 @@ class replica_bitline(design.design):
         # DRAIN ROUTE
         # Route the drain to the vdd rail
         drain_offset = self.tx_inst.get_pin("D").center()
-        self.add_power_pin("vdd", drain_offset)
+        self.add_power_pin("vdd", drain_offset, rotate=0)
         
         # SOURCE ROUTE
         # Route the drain to the RBL inverter input 
diff --git a/compiler/pgates/pbitcell.py b/compiler/pgates/pbitcell.py
index b02ceee1..5816e350 100644
--- a/compiler/pgates/pbitcell.py
+++ b/compiler/pgates/pbitcell.py
@@ -222,9 +222,9 @@ class pbitcell(design.design):
         self.rowline_spacing = self.m1_space + contact.m1m2.width
         
         # spacing for vdd
-        vdd_offset_well_constraint = self.well_enclose_active + 0.5*contact.well.width
-        vdd_offset_metal1_constraint = max(inverter_pmos_contact_extension, 0) + self.m1_space + 0.5*contact.well.width
-        self.vdd_offset = max(vdd_offset_well_constraint, vdd_offset_metal1_constraint)
+        implant_constraint = max(inverter_pmos_contact_extension, 0) + 2*self.implant_enclose_active + 0.5*(contact.well.width - self.m1_width)
+        metal1_constraint = max(inverter_pmos_contact_extension, 0) + self.m1_space
+        self.vdd_offset = max(implant_constraint, metal1_constraint)  + 0.5*self.m1_width
         
         # read port dimensions
         width_reduction = self.read_nmos.active_width - self.read_nmos.get_pin("D").cx()
@@ -334,7 +334,7 @@ class pbitcell(design.design):
                                                    layer="metal1",
                                                    offset=self.gnd_position,
                                                    width=self.width,
-                                                   height=contact.well.second_layer_width)
+                                                   height=self.m1_width)
         
         vdd_ypos = self.inverter_nmos_ypos + self.inverter_nmos.active_height + self.inverter_gap + self.inverter_pmos.active_height + self.vdd_offset
         self.vdd_position = vector(0, vdd_ypos)
@@ -342,7 +342,7 @@ class pbitcell(design.design):
                                                    layer="metal1",
                                                    offset=self.vdd_position,
                                                    width=self.width,
-                                                   height=contact.well.second_layer_width)
+                                                   height=self.m1_width)
 
     def create_readwrite_ports(self):
         """
@@ -933,8 +933,9 @@ class pbitcell(design.design):
         
     def route_rbc_short(self):
         """ route the short from Q_bar to gnd necessary for the replica bitcell """
-        Q_bar_pos = self.inverter_pmos_right.get_pin("S").uc()
-        vdd_pos = vector(Q_bar_pos.x, self.vdd_position.y)
+        Q_bar_pos = self.inverter_pmos_right.get_pin("S").center()
+        vdd_pos = self.inverter_pmos_right.get_pin("D").center()
+        #vdd_pos = vector(Q_bar_pos.x, self.vdd_position.y)
         
         self.add_path("metal1", [Q_bar_pos, vdd_pos])
         
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