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ommit rbl pins in sram_1bank when appropriate

This commit is contained in:
Sam Crow 2023-06-06 13:15:17 -07:00
parent 157935c915
commit 9fdf8a8341
1 changed files with 7 additions and 3 deletions
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10
compiler/modules/sram_1bank.py
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@ -50,6 +50,9 @@ class sram_1bank(design, verilog, lef):
# Route a M3/M4 grid # Route a M3/M4 grid
self.supply_stack = self.m3_stack self.supply_stack = self.m3_stack
# delay control logic does not have RBLs
self.has_rbl = OPTS.control_logic != "control_logic_delay"
def add_pins(self): def add_pins(self):
""" Add pins for entire SRAM. """ """ Add pins for entire SRAM. """
@ -517,8 +520,9 @@ class sram_1bank(design, verilog, lef):
for port in self.read_ports: for port in self.read_ports:
for bit in range(self.word_size + self.num_spare_cols): for bit in range(self.word_size + self.num_spare_cols):
temp.append("dout{0}[{1}]".format(port, bit)) temp.append("dout{0}[{1}]".format(port, bit))
for port in self.all_ports: if self.has_rbl:
temp.append("rbl_bl{0}".format(port)) for port in self.all_ports:
temp.append("rbl_bl{0}".format(port))
for port in self.write_ports: for port in self.write_ports:
for bit in range(self.word_size + self.num_spare_cols): for bit in range(self.word_size + self.num_spare_cols):
temp.append("bank_din{0}_{1}".format(port, bit)) temp.append("bank_din{0}_{1}".format(port, bit))
@ -693,7 +697,7 @@ class sram_1bank(design, verilog, lef):
if port in self.readwrite_ports: if port in self.readwrite_ports:
temp.append("web{}".format(port)) temp.append("web{}".format(port))
temp.append("clk{}".format(port)) temp.append("clk{}".format(port))
if OPTS.control_logic != "control_logic_delay": if self.has_rbl:
temp.append("rbl_bl{}".format(port)) temp.append("rbl_bl{}".format(port))
# Outputs # Outputs