From 9fdf8a8341054f8874432c9300a574e1b6f92e4a Mon Sep 17 00:00:00 2001 From: Sam Crow Date: Tue, 6 Jun 2023 13:15:17 -0700 Subject: [PATCH] ommit rbl pins in sram_1bank when appropriate --- compiler/modules/sram_1bank.py | 10 +++++++--- 1 file changed, 7 insertions(+), 3 deletions(-) diff --git a/compiler/modules/sram_1bank.py b/compiler/modules/sram_1bank.py index 6ad45ee3..9f26e2eb 100644 --- a/compiler/modules/sram_1bank.py +++ b/compiler/modules/sram_1bank.py @@ -50,6 +50,9 @@ class sram_1bank(design, verilog, lef): # Route a M3/M4 grid self.supply_stack = self.m3_stack + # delay control logic does not have RBLs + self.has_rbl = OPTS.control_logic != "control_logic_delay" + def add_pins(self): """ Add pins for entire SRAM. """ @@ -517,8 +520,9 @@ class sram_1bank(design, verilog, lef): for port in self.read_ports: for bit in range(self.word_size + self.num_spare_cols): temp.append("dout{0}[{1}]".format(port, bit)) - for port in self.all_ports: - temp.append("rbl_bl{0}".format(port)) + if self.has_rbl: + for port in self.all_ports: + temp.append("rbl_bl{0}".format(port)) for port in self.write_ports: for bit in range(self.word_size + self.num_spare_cols): temp.append("bank_din{0}_{1}".format(port, bit)) @@ -693,7 +697,7 @@ class sram_1bank(design, verilog, lef): if port in self.readwrite_ports: temp.append("web{}".format(port)) temp.append("clk{}".format(port)) - if OPTS.control_logic != "control_logic_delay": + if self.has_rbl: temp.append("rbl_bl{}".format(port)) # Outputs