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Fix capitalization in verilog golden files

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This commit is contained in:
Matt Guthaus
2019-08-21 14:29:57 -07:00
parent 5f3ffdb8ba
commit 9f54afbf2c
12 changed files with 54 additions and 54 deletions
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compiler/tests/golden/sram_2_16_1_freepdk45.v
+10 -10
View File
@@ -7,24 +7,24 @@ module sram_2_16_1_freepdk45(
clk0,csb0,web0,addr0,din0,dout0
);
parameter data_WIDTH = 2 ;
parameter addr_WIDTH = 4 ;
parameter RAM_DEPTH = 1 << addr_WIDTH;
parameter DATA_WIDTH = 2 ;
parameter ADDR_WIDTH = 4 ;
parameter RAM_DEPTH = 1 << ADDR_WIDTH;
// FIXME: This delay is arbitrary.
parameter DELAY = 3 ;
input clk0; // clock
input csb0; // active low chip select
input web0; // active low write control
input [addr_WIDTH-1:0] addr0;
input [data_WIDTH-1:0] din0;
output [data_WIDTH-1:0] dout0;
input [ADDR_WIDTH-1:0] addr0;
input [DATA_WIDTH-1:0] din0;
output [DATA_WIDTH-1:0] dout0;
reg csb0_reg;
reg web0_reg;
reg [addr_WIDTH-1:0] addr0_reg;
reg [data_WIDTH-1:0] din0_reg;
reg [data_WIDTH-1:0] dout0;
reg [ADDR_WIDTH-1:0] addr0_reg;
reg [DATA_WIDTH-1:0] din0_reg;
reg [DATA_WIDTH-1:0] dout0;
// All inputs are registers
always @(posedge clk0)
@@ -40,7 +40,7 @@ module sram_2_16_1_freepdk45(
$display($time," Writing %m addr0=%b din0=%b",addr0_reg,din0_reg);
end
reg [data_WIDTH-1:0] mem [0:RAM_DEPTH-1];
reg [DATA_WIDTH-1:0] mem [0:RAM_DEPTH-1];
// Memory Write Block Port 0
// Write Operation : When web0 = 0, csb0 = 0
compiler/tests/golden/sram_2_16_1_scn4m_subm.v
+10 -10
View File
@@ -7,24 +7,24 @@ module sram_2_16_1_scn4m_subm(
clk0,csb0,web0,addr0,din0,dout0
);
parameter data_WIDTH = 2 ;
parameter addr_WIDTH = 4 ;
parameter RAM_DEPTH = 1 << addr_WIDTH;
parameter DATA_WIDTH = 2 ;
parameter ADDR_WIDTH = 4 ;
parameter RAM_DEPTH = 1 << ADDR_WIDTH;
// FIXME: This delay is arbitrary.
parameter DELAY = 3 ;
input clk0; // clock
input csb0; // active low chip select
input web0; // active low write control
input [addr_WIDTH-1:0] addr0;
input [data_WIDTH-1:0] din0;
output [data_WIDTH-1:0] dout0;
input [ADDR_WIDTH-1:0] addr0;
input [DATA_WIDTH-1:0] din0;
output [DATA_WIDTH-1:0] dout0;
reg csb0_reg;
reg web0_reg;
reg [addr_WIDTH-1:0] addr0_reg;
reg [data_WIDTH-1:0] din0_reg;
reg [data_WIDTH-1:0] dout0;
reg [ADDR_WIDTH-1:0] addr0_reg;
reg [DATA_WIDTH-1:0] din0_reg;
reg [DATA_WIDTH-1:0] dout0;
// All inputs are registers
always @(posedge clk0)
@@ -40,7 +40,7 @@ module sram_2_16_1_scn4m_subm(
$display($time," Writing %m addr0=%b din0=%b",addr0_reg,din0_reg);
end
reg [data_WIDTH-1:0] mem [0:RAM_DEPTH-1];
reg [DATA_WIDTH-1:0] mem [0:RAM_DEPTH-1];
// Memory Write Block Port 0
// Write Operation : When web0 = 0, csb0 = 0