luke/OpenRAM
1
0
Fork 0
mirror of https://github.com/VLSIDA/OpenRAM.git synced 2026-08-30 01:48:33 +02:00
Code Issues Packages Projects Releases Wiki Activity

Fix capitalization in verilog golden files

Browse Source
This commit is contained in:
Matt Guthaus
2019-08-21 14:29:57 -07:00
parent 5f3ffdb8ba
commit 9f54afbf2c
12 changed files with 54 additions and 54 deletions
Download Patch File Download Diff File Expand all files Collapse all files
compiler/modules/bank.py
+1 -1
View File
@@ -30,7 +30,7 @@ class bank(design.design):
self.sram_config = sram_config
sram_config.set_local_config(self)
if self.write_size is not None:
if self.write_size:
self.num_wmasks = int(self.word_size/self.write_size)
else:
self.num_wmasks = 0
compiler/modules/multibank.py
+1 -1
View File
@@ -187,7 +187,7 @@ class multibank(design.design):
words_per_row=self.words_per_row)
self.add_mod(self.sense_amp_array)
if self.write_size is not None:
if self.write_size:
self.write_mask_driver_array = self.mod_write_mask_driver_array(columns=self.num_cols,
word_size=self.word_size,
write_size=self.write_size)
compiler/modules/port_data.py
+4 -4
View File
@@ -22,7 +22,7 @@ class port_data(design.design):
sram_config.set_local_config(self)
self.port = port
if self.write_size is not None:
if self.write_size:
self.num_wmasks = int(self.word_size/self.write_size)
else:
self.num_wmasks = 0
@@ -58,7 +58,7 @@ class port_data(design.design):
if self.write_driver_array:
self.create_write_driver_array()
if self.write_size is not None:
if self.write_size:
self.create_write_mask_and_array()
else:
self.write_mask_and_array_inst = None
@@ -183,7 +183,7 @@ class port_data(design.design):
word_size=self.word_size,
write_size=self.write_size)
self.add_mod(self.write_driver_array)
if self.write_size is not None:
if self.write_size:
self.write_mask_and_array = factory.create(module_type="write_mask_and_array",
columns=self.num_cols,
word_size=self.word_size,
@@ -316,7 +316,7 @@ class port_data(design.design):
temp.append(self.bl_names[self.port]+"_out_{0}".format(bit))
temp.append(self.br_names[self.port]+"_out_{0}".format(bit))
if self.write_size is not None:
if self.write_size:
for i in range(self.num_wmasks):
temp.append("wdriver_sel_{}".format(i))
else:
compiler/modules/write_driver_array.py
+2 -2
View File
@@ -30,7 +30,7 @@ class write_driver_array(design.design):
self.write_size = write_size
self.words_per_row = int(columns / word_size)
if self.write_size is not None:
if self.write_size:
self.num_wmasks = int(self.word_size/self.write_size)
self.create_netlist()
@@ -89,7 +89,7 @@ class write_driver_array(design.design):
self.driver_insts[index]=self.add_inst(name=name,
mod=self.driver)
if self.write_size is not None:
if self.write_size:
self.connect_inst(["data_{0}".format(index),
"bl_{0}".format(index),
"br_{0}".format(index),