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https://github.com/VLSIDA/OpenRAM.git
synced 2026-09-03 05:33:56 +02:00
Fix capitalization in verilog golden files
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@@ -34,7 +34,7 @@ class functional(simulation):
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if OPTS.is_unit_test:
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random.seed(12345)
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if self.write_size is not None:
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if self.write_size:
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self.num_wmasks = int(self.word_size / self.write_size)
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else:
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self.num_wmasks = 0
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@@ -61,7 +61,7 @@ class functional(simulation):
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def initialize_wmask(self):
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self.wmask = ""
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if self.write_size is not None:
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if self.write_size:
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# initialize all wmask bits to 1
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for bit in range(self.num_wmasks):
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self.wmask += "1"
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@@ -85,7 +85,7 @@ class functional(simulation):
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return self.check_stim_results()
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def write_random_memory_sequence(self):
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if self.write_size is not None:
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if self.write_size:
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rw_ops = ["noop", "write", "partial_write", "read"]
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w_ops = ["noop", "write", "partial_write"]
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else:
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@@ -340,7 +340,7 @@ class functional(simulation):
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# Generate wmask bits
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for port in self.write_ports:
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if self.write_size is not None:
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if self.write_size:
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self.sf.write("\n* Generation of wmask signals\n")
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for bit in range(self.num_wmasks):
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sig_name = "WMASK{0}_{1} ".format(port, bit)
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