Add separate well design rules.

Needed to fix various pgates with wells.
Did some cleanup of these gates as well.

technology/freepdk45/tech/tech.py

@@ -145,7 +145,10 @@ drc["minlength_channel"] = 0.05
 drc["pwell_to_nwell"] = 0.225
 # WELL.3 Minimum spacing of nwell/pwell at the same potential
 # WELL.4 Minimum width of nwell/pwell
-drc.add_layer("well",
+drc.add_layer("nwell",
+              width = 0.2,
+              spacing = 0.135)
+drc.add_layer("pwell",
               width = 0.2,
               spacing = 0.135)
 
@@ -174,7 +177,10 @@ drc.add_layer("active",
               width = 0.09,
               spacing = 0.08)
 # ACTIVE.3 Minimum enclosure/spacing of nwell/pwell to active
-drc.add_enclosure("well",
+drc.add_enclosure("nwell",
+                  layer = "active",
+                  enclosure = 0.055)
+drc.add_enclosure("pwell",
                   layer = "active",
                   enclosure = 0.055)
 

technology/scn4m_subm/tech/tech.py

@@ -126,11 +126,14 @@ drc["layer_map"]=os.environ.get("OPENRAM_TECH")+"/scn3me_subm/layers.map"
 drc["minwidth_tx"] = 4*_lambda_
 drc["minlength_channel"] = 2*_lambda_
 
-# 1.4 Minimum spacing between wells of different type (if both are drawn) 
+# 1.4 Minimum spacing between wells of different type (if both are drawn)
 drc["pwell_to_nwell"] = 0
 # 1.3 Minimum spacing between wells of same type (if both are drawn)
-# 1.1 Minimum width 
-drc.add_layer("well",
+# 1.1 Minimum width
+drc.add_layer("nwell",
+              width = 12*_lambda_,
+              spacing = 6*_lambda_)
+drc.add_layer("pwell",
               width = 12*_lambda_,
               spacing = 6*_lambda_)
 
@@ -157,7 +160,10 @@ drc.add_layer("active",
               spacing = 4*_lambda_)
 
 # 2.3 Source/drain active to well edge 
-drc.add_enclosure("well",
+drc.add_enclosure("nwell",
+                  layer = "active",
+                  enclosure = 6*_lambda_)
+drc.add_enclosure("pwell",
                   layer = "active",
                   enclosure = 6*_lambda_)