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Add separate well design rules.

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Needed to fix various pgates with wells.
Did some cleanup of these gates as well.
This commit is contained in:
mrg
2020-01-23 19:43:41 +00:00
parent 306740f0f3
commit 9beb0f4ece
16 changed files with 181 additions and 111 deletions
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compiler/modules/bank.py
+1 -1
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@@ -333,7 +333,7 @@ class bank(design.design):
self.col_addr_bus_width = self.m2_pitch*self.num_col_addr_lines
# A space for wells or jogging m2
self.m2_gap = max(2*drc("pwell_to_nwell") + drc("well_enclose_active"),
self.m2_gap = max(2*drc("pwell_to_nwell") + drc("nwell_enclose_active"),
3*self.m2_pitch)
compiler/modules/port_address.py
+1 -1
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@@ -149,7 +149,7 @@ class port_address(design.design):
"""
# A space for wells or jogging m2
self.m2_gap = max(2*drc("pwell_to_nwell") + drc("well_enclose_active"),
self.m2_gap = max(2*drc("pwell_to_nwell") + drc("nwell_enclose_active"),
3*self.m2_pitch)
row_decoder_offset = vector(0,0)
compiler/modules/port_data.py
+1 -1
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@@ -212,7 +212,7 @@ class port_data(design.design):
# A space for wells or jogging m2 between modules
self.m2_gap = max(2*drc("pwell_to_nwell") + drc("well_enclose_active"),
self.m2_gap = max(2*drc("pwell_to_nwell") + drc("nwell_enclose_active"),
3*self.m2_pitch)